Nonplanar iii-n transistors with compositionally graded semiconductor channels

A non-planar III-N transistor disposed on a substrate, the transistor comprising:

• two wide band gap material layers on opposite sides of a III-N semiconductor channel that has a compositional grading along the c-axis between the two wide band gap crystalline material layers;
• a gate stack comprising a gate dielectric and gate electrode, the gate stack disposed over opposing surfaces of the semiconductor channel that span a distance between the two wide band gap material layers;
• and
• a pair of source/drain regions embedded in or coupled to the non-planar III-N semiconductor body at opposite sides of the gate stack.
• wherein a transport channel is formed in the III-N semiconductor channel adjacent to both opposing surfaces in response to a bias voltage on a gate electrode exceeding a threshold voltage of the transistor.