Structure And Method For Integrated Devices On Different Substartes With Interfacial Engineering
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLiang-Gi Yao, I-Ming Chang, Yasutoshi Okuno, Chih-Hao Chang, Shou Zen Chang, Clement Hsingien Wann
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Abstract
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first semiconductor material and a first reactivity; and a low reactivity capping layer of disposed on the semiconductor substrate, wherein the low reactivity capping layer includes a second semiconductor material and a second reactivity less than the first reactivity, the low reactivity capping layer includes silicon germanium Si1−xGex and x is less than about 30%.
Claims21
A semiconductor structure, comprising:
- a substrate having a first semiconductor material layer with a first reactivity;
- and
- a low reactivity capping layer disposed on the substrate, wherein the low reactivity capping layer has a second reactivity less than the first reactivity, and the low reactivity capping layer includes silicon germanium Si1−xGex and x is less than about 30%.
A semiconductor structure, comprising:
- a substrate;
- a first semiconductor layer disposed on the substrate, wherein the first semiconductor layer includes silicon germanium Si1−xGex and x is greater than about 40%;
- and
- a second semiconductor layer disposed on the first semiconductor layer, wherein the second semiconductor layer includes one of silicon and silicon germanium Si1−yGey with y being less than about 30%.
16-20. (canceled)
An integrated circuit device, comprising:
- a first semiconductor layer on a substrate, wherein the first semiconductor layer includes silicon germanium Si1−xGex and x is greater than about 40%;
- a second semiconductor layer on the first semiconductor layer, wherein the second semiconductor layer includes silicon germanium Si1−yGey and y is less than about 30%;
- and
- an interlayer dielectric (ILD) layer on the second semiconductor layer;
The device of claim 18, further comprising:
- a third semiconductor layer in the trench.
The device of claim 18, wherein the gate stack includes
- a high-k dielectric material layer;
- and
- a metal layer on the high-k dielectric material layer.
The device of claim 18, wherein the second semiconductor layer has a thickness less than about 2 nm.
Dependencies are inferred from the claim text.