Field-effect transistor

A field-effect transistor comprising:

• a semiconductor laminated structure comprising a first semiconductor layer formed of a first nitride semiconductor, a second semiconductor layer formed of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor, and a two-dimensional electron gas layer generated at an interface on the second semiconductor layer side of the first semiconductor layer;
• a source electrode;
• a drain electrode;
• and
• a gate electrode disposed over the second semiconductor layer, the gate electrode being adapted to control the flow of electrons passing through the two-dimensional electron gas layer between the source electrode and the drain electrode;
• a third semiconductor layer formed of a p-type nitride semiconductor containing p-type dopant between the gate electrode and the second semiconductor layer;
• and
• a fourth semiconductor layer formed of a nitride semiconductor between the third semiconductor layer and the gate electrode,
• wherein the fourth semiconductor layer is in contact with the gate electrode,
• wherein the fourth semiconductor layer has a larger bandgap than that of the third semiconductor layer, and a small concentration of p-type dopant, and
• wherein the fourth semiconductor layer has a concentration of n-type dopant of 1×1017 cm−3 or less, or does not contain n-type dopant.

A field-effect transistor comprising:

• a semiconductor laminated structure including a first semiconductor layer formed of a first nitride semiconductor, a second semiconductor layer formed of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor, and a two-dimensional electron gas layer generated at an interface on the second semiconductor layer side of the first semiconductor layer;
• a source electrode;
• a drain electrode;
• a gate electrode disposed over the second semiconductor layer, the gate electrode being adapted to control the flow of electrons passing through the two-dimensional electron gas layer between the source electrode and the drain electrode;
• a third semiconductor layer formed of a p-type nitride semiconductor containing p-type dopant between the gate electrode and the second semiconductor layer;
• and
• a fourth semiconductor layer formed of a nitride semiconductor between the third semiconductor layer and the gate electrode,
• wherein the fourth semiconductor layer is in contact with the gate electrode,
• wherein the fourth semiconductor layer has a larger bandgap than that of the third semiconductor layer, and
• wherein the fourth semiconductor layer is formed of a p-type nitride semiconductor with a small concentration of p-type dopant or an i-type nitride semiconductor.

A method of manufacturing a field-effect transistor comprising:

• a step of forming a semiconductor laminated structure, the semiconductor laminated structure including a first semiconductor layer formed of a first nitride semiconductor, a second semiconductor layer formed of a second nitride semiconductor having a bandgap energy larger than that of the first nitride semiconductor, and a two-dimensional electron gas layer generated at an interface on the second semiconductor layer side of the first semiconductor layer;
• a step of forming a third semiconductor layer using a p-type nitride semiconductor over the second semiconductor layer, while supplying p-type dopant;
• a step of forming a fourth semiconductor layer using a p-type or i-type nitride semiconductor over the third semiconductor layer, while supplying p-type dopant in a smaller amount than that in the third semiconductor layer forming step, or without supplying any dopant, said fourth semiconductor layer having a larger bandgap than that of the third semiconductor layer;
• and
• a step of forming a source electrode, a drain electrode, and a gate electrode adapted to control the flow of electrons passing through the two-dimensional electron gas layer between the source electrode and the drain electrode, said gate electrode being in contact with an upper surface of the fourth semiconductor layer.