Devices and systems for power conversion circuits

A system comprising:

• a cascode arrangement of a HV normally on GaN transistor, the driver MOSFET comprising a low voltage lateral N-channel MOSFET fabricated on a silicon substrate, the GaN transistor being fabricated on a first substrate (GaN die) and the driver MOSFET being fabricated on a second substrate (CMOS die);
• and
• the CMOS die and the GaN die being stacked in a flip-chip configuration to provide a plurality of direct interconnects between the drain of the driver MOSFET and the source of the GaN HEMT and a plurality of direct interconnects between the source of the driver MOSFET and the gate of the GaN HEMT.

A normally-off N channel driver MOSFET for a system comprising a cascode arrangement of a HV normally on GaN transistor, the driver MOSFET comprising:

• a lateral N-channel MOSFET fabricated on a silicon substrate (CMOS die), and comprising an array of a plurality of alternating source and drain regions defined on an active region of the silicon substrate, channel regions extending between the source and drain regions, and an interconnect structure comprising respective source, drain and gate contacts,
• a plurality of Through Substrate Vias (TSV) connecting the source contacts to a back-side source electrode of the CMOS die, and wherein drain and gate contacts of the driver MOSFET comprise an arrangement of a plurality of front-side contact areas of the CMOS die.

A driver for a system comprising a cascode arrangement of a HV normally on GaN transistor and a normally-off N-channel driver MOSFET comprising:

• a CMOS substrate (CMOS die) comprising a CMOS driver circuit and an integrated driver MOSFET, wherein the driver MOSFET comprises:
• a lateral N-channel MOSFET fabricated on a silicon substrate (CMOS die) and comprising an array of a plurality of alternating source and drain regions defined on an active region of the silicon substrate, channel regions extending between the source and drain regions, and an interconnect structure comprising respective source, drain and gate contacts,
• a plurality of Through Substrate Vias (TSV) connecting the source contacts to a back-side source electrode of the CMOS die, and wherein drain and gate contacts of the driver MOSFET comprise an arrangement of a plurality of front-side contact areas of the CMOS die.