Semiconductor integrated circuit and multi-chip package including the same
AssigneeSK hynix Inc.
InventorTae-Yong LEE
Life of this patent
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Abstract
In an aspect of the present invention, a semiconductor integrated circuit includes a semiconductor chip including a through-chip via, a probe pad disposed in such a way as not to overlap with the through-chip via, and a connection part electrically coupling the probe pad and the through-chip via
Claims16
A semiconductor integrated circuit comprising:
- a semiconductor chip including a through-chip via;
- a probe pad disposed not to overlap the through-chip via;
- and
- a connection part configured to electrically couple the probe pad and the through-chip via.
A multi-chip package, comprising:
- a plurality of semiconductor chips, each including a number of through-chip vias;
- bumps configured to be overlapped with the respective through-chip vias and electrically couple the plurality of semiconductor chips;
- probe pads disposed not to overlap the respective bumps;
- and
- connection parts configured to electrically couple the probe pads and the through-chip vias.
The multi-chip package of claim wherein the plurality of semiconductor chips are spaced apart from each other at an interval corresponding to a size of the bumps.
The multi-chip package of claim wherein the connection parts are configured to be connected or disconnected to the probe pads and the through-chip vias.
A multi-chip package, comprising:
- a plurality of semiconductor chips including a plurality of through-chip vias;
- a probe pad coupled to a number of through-chip vias with the through-chip vias, wherein the probe pad includes a probe region having a predetermined area and regions other than the probe region;
- and
- a plurality of bumps, each bump coupled to the corresponding through-via other than the probe region and electrically coupled to the through-chip vias.
A semiconductor integrated circuit comprising:
- a semiconductor chip including a plurality of through-chip vias;
- and
- a plurality of probe pads, each probe pad configured to be contacted by a probe pin and electrically coupling a predetermined number of the through-chip vias.
Dependencies are inferred from the claim text.