Thin film transistor array panel and method of manufacturing the same

A method of manufacturing a thin film transistor array panel, comprising:

• forming an oxide semiconductor layer on an insulation substrate;
• forming an insulating layer and a gate line comprising a gate electrode on the oxide semiconductor layer;
• forming a channel layer, a source electrode, a drain electrode, and a pixel electrode in the oxide semiconductor layer by performing a reduction process on an exposed portion of the oxide semiconductor layer,
• wherein the channel layer is covered by the gate electrode, the source electrode is formed at a first side of the channel layer, the drain electrode is formed at a second side of the channel layer, opposing the first side, the pixel electrode and the drain electrode are formed in a same portion of the oxide semiconductor layer, and the exposed portion of the oxide semiconductor layer is not covered by the insulating layer and the gate line;
• forming a passivation layer on the source electrode, the drain electrode, the pixel electrode, and the gate line;
• and
• forming a data line on the passivation layer,
• wherein a width of the channel layer is formed to be substantially equal to a width of the pixel electrode in a direction parallel to the gate line.