Tunneling transistor
AssigneesGlobalfoundries Singapore Pte. Ltd., National University of Singapore
InventorsKian Hui GOH, Eng Huat TOH, Yee Chia YEO
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Abstract
Devices and methods for forming a device are presented. The device includes a substrate and a fin type transistor disposed on the substrate. The transistor includes a fin structure which serves as a body of the transistor. The fin structure includes first and second end regions and an intermediate region in between the first and second end regions. A source region is disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure. The device includes a channel region disposed adjacent to the source region and a gate dielectric of the gate. A source tunneling junction is aligned to the gate with a controlled channel thickness TCH.
Claims20
A device comprising:
- a substrate;
- and
- a fin-type transistor disposed on the substrate, wherein the transistor comprises
- a fin structure which serves as a body of the transistor, wherein the fin structure includes first and second end regions and an intermediate region in between the first and second end regions of the fin structure,
- a source region disposed on the first end region, a drain region disposed in the second end region and a gate disposed on the intermediate region of the fin structure, and
- a channel region disposed adjacent to the source region and a gate dielectric of the gate, wherein a source tunneling junction is aligned to the gate with a controlled channel thickness TCH.
A method for forming a device comprising:
- providing a substrate;
- and
- forming a fin-type transistor on the substrate, wherein forming the transistor comprises
- forming a fin structure having a shape, wherein the fin structure includes first and second end regions and an intermediate region in between the first and second end regions of the fin structure and the fin structure serves as a body of the transistor,
- forming a source region on the first end region, a drain region in the second end region and a gate on the intermediate region of the fin structure, and
- forming a channel region adjacent to the source region and a gate dielectric of the gate, wherein a source tunneling junction is aligned to the gate with a controlled channel thickness TCH.
Dependencies are inferred from the claim text.