Hybrid cmos nanowire mesh device and pdsoi device

A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:

• a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one partially depleted semiconductor on insulator (PDSOI) device;
• the at least one nanowire mesh device comprising:
• a plurality of stacked and spaced apart semiconductor nanowires located on the SOI substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
• and a gate region over at least a portion of the plurality of stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
• the at least one PDSOI device comprising:
• a partially depleted semiconductor layer on the substrate;
• and a gate region and a gate conductor over at least a portion of the partially depleted semiconductor layer.

An integrated circuit comprising:

• a semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate, the semiconductor hybrid structure comprising:
• first portions of the SOI substrate containing a plurality of nanowire mesh devices and second portions of the SOI substrate containing a plurality of partially depleted semiconductor on insulator (PDSOI) devices;
• each of the plurality of nanowire mesh devices comprising:
• a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the SOI substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
• and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
• each of the plurality of PDSOI devices comprising:
• a partially depleted semiconductor layer on the SOI substrate;
• and a gate region including a gate dielectric and a gate conductor over at least a portion of the partially depleted semiconductor layer.