Hybrid cmos nanowire mesh device and finfet device

A semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate comprising:

• a first portion of the SOI substrate containing at least one nanowire mesh device and a second portion of the SOI substrate containing at least one FINFET device;
• the at least one nanowire mesh device comprising:
• a plurality of stacked and spaced apart semiconductor nanowires located on the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
• and a gate region over at least a portion of the plurality of stacked and spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
• the at least one FINFET device comprising:
• a plurality of spaced apart fins on a top semiconductor layer on the second portion of the substrate;
• and a gate region over at least a portion of the plurality of fins.

An integrated circuit comprising:

• a semiconductor hybrid structure on a semiconductor on insulator (SOI) substrate, the semiconductor hybrid structure comprising:
• first portions of the SOI substrate containing a plurality of nanowire mesh devices and second portions of the SOI substrate containing a plurality of FINFET devices;
• each of the plurality of nanowire mesh devices comprising:
• a plurality of vertically stacked and vertically spaced apart semiconductor nanowires located on a surface of the substrate, each semiconductor nanowire having two end segments in which one of the end segments is connected to a source region and the other end segment is connected to a drain region;
• and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of vertically stacked and vertically spaced apart semiconductor nanowires, wherein each source region and each drain region is self-aligned with the gate region;
• each of the plurality of FINFET devices comprising:
• a plurality of spaced apart fins on a top semiconductor layer on the second portion of the substrate;
• and a gate region including a gate dielectric and a gate conductor over at least a portion of the plurality of fins.