Resistive random access memory (rram) structure and method of making the rram structure

A method of making a logic device having embedded resistive random access memory (RRAM) cells, the method comprising:

• forming shallow trench isolation (STI) regions in a semiconductor substrate;
• depositing a gate dielectric;
• depositing a gate material over the gate dielectric;
• patterning the gate dielectric and the gate material into a transistor gate and a bottom electrode, wherein at least a portion of the bottom electrode is disposed over a portion of the STI regions;
• forming a source region and a drain region adjacent to the transistor gate;
• depositing a first dielectric material layer;
• depositing a layer of top electrode material on the first dielectric material layer;
• patterning the first dielectric material and the top electrode into a RRAM structure;
• depositing an interlayer dielectric (ILD);
• and
• forming a bit line contact through the ILD to the source region and a stretch contact through the ILD to connect the bottom electrode and the drain region.

A method of making a logic device having embedded resistive random access memory (RRAM) cells, the method comprising:

• forming a transistor having a gate, a source region, and a drain region;
• forming a bottom electrode adjacent to the drain region and coplanar with the gate;
• depositing a resistive material layer on the bottom electrode;
• forming a top electrode on the resistive material layer;
• and
• depositing a conductive material connecting the bottom electrode to the drain region.