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US 2014/0173391 A1Published application
Measured value transmitting device
AssigneeBalluff GmbH
InventorUwe Hahn
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AssigneeBalluff GmbH
InventorUwe Hahn
Estimating the term…
The invention relates to measured value transmitting devices for serially transmitting data in accordance with the SSI method, Synchronous Serial Interface. At least one slave is provided which provides the data bits of a measured value detected by at least one sensor for the purpose of a serial bit-by-bit transmission to a master. The master requests a measured value from the slave by means of a clock burst that has multiple clock cycles, the number of which matches the number of the data bits to be transmitted. A first measured value transmitting device according to the invention is characterized in that the clock cycles of the clock burst have a specified duty cycle which corresponds to the ratio of the pulse duration to the period duration of one clock cycle, and the master contains a comparator. The master reads the clock bursts outputted on the at least one clock line and checks the duty cycle in the comparator to determine whether an upper threshold and/or a lower threshold has been exceeded. A second measured value transmitting device according to the invention is characterized in that a corresponding check of the duty cycle is carried out in the slave.
A measured value transmitting device for serial data transmission from at least one slave (SL) which provides the data bits (DB) of a measured value (14) detected by at least one sensor (12) for the purpose of serial bit-by-bit transmission to a master (MA) on at least one data line (28), and in which the master (MA) requests a measured value (14) from the slave (SL) by means of a clock burst (20, 20+, 20−) which is provided on at least one clock line (26, 60, 62) and which comprises several clock cycles (ZCLK, ZCLK+, ZCLK−), the number of which (n+1) matches the number (n) of the data bits (DB) to be transmitted, wherein the clock cycles (ZCLK, ZCLK+, ZCLK−) of the clock burst (20, 20+, 20−) have a specified duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) which corresponds to the ratio of pulse duration (TLow, TLow+, TLow−) to the period duration (TCLK, TCLK+, TCLK−) of one clock cycle (ZCLK, ZCLK+, ZCLK−), and the master (MA) contains a comparator (32, 70), and said master MA) reads back the clock bursts (20, 20+, 20−) outputted on the at least one clock line (26, 60, 62) and checks the duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) in the comparator (32, 70) to determine whether said cycle exceeds an upper threshold (34) and/or falls below a lower threshold (36).
A measured value transmitting device for serial data transmission from at least one slave (SL) which provides the data bits (DB) of a measured value (14) detected by at least one sensor (12) for the purpose of serial bit-by-bit transmission to a master (MA) on at least one data line (28), and in which the master (MA) requests a measured value (14) from the slave (SL) by means of a clock burst (20, 20+, 20−) which is provided on at least one clock line (26, 60, 62) and which comprises several clock cycles (ZCLK, ZCLK+, ZCLK−), the number of which (n+1) matches the number (n) of the data bits (DB) to be transmitted, wherein the clock cycles (ZCLK, ZCLK+, ZCLK−) of the clock burst (20, 20+, 20−) have a specified duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) which corresponds to the ratio of pulse duration (TLow, TLow+, TLow−) to the period duration (TCLK, TCLK+, TCLK−) of one clock cycle (ZCLK, ZCLK+, ZCLK−), and the slave (SL) contains a comparator (42, 72) and checks the duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) in the comparator (42, 72) to determine whether said cycle exceeds an upper threshold (44) and/or falls below a lower threshold (46).
A measured value transmitting device for serial data transmission from at least one slave (SL) which provides the data bits (DB) of a measured value (14) detected by at least one sensor (12) for the purpose of serial bit-by-bit transmission to a master (MA) on at least one data line (28), and in which the master (MA) requests a measured value (14) from the slave (SL) by means of a clock burst (20, 20+, 20−) which is provided on at least one clock line (26, 60, 62) and which comprises several clock cycles (ZCLK, ZCLK+, ZCLK−), the number of which (n+1) matches the number (n) of the data bits (DB) to be transmitted, wherein the clock cycles (ZCLK, ZCLK+, ZCLK−) of the clock burst (20, 20+, 20−) have a specified duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) which corresponds to the ratio of pulse duration (TLow, TLow+, TLow−) to the period duration (TCLK, TCLK+, TCLK−) of one clock cycle (ZCLK, ZCLK+, ZCLK−), and the master (MA) contains a comparator (32, 70), and said master MA) reads back the clock bursts (20, 20+, 20−) outputted on the at least one clock line (26, 60, 62) and checks the duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) in the comparator (32, 70) to determine whether said cycle exceeds an upper threshold (34) and/or falls below a lower threshold (36), and the slave (SL) contains a comparator (42, 72) and checks the duty cycle (TLow/TCLK, TLow+/TCLK+, TLow−/TCLK−) in the comparator (42, 72) to determine whether said cycle exceeds an upper threshold (44) and/or falls below a lower threshold (46).
Dependencies are inferred from the claim text.