# US 2014/0157397 A1 · Efficient packet handling, redirection, and inspection using offload processors

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- Number: US 2014/0157397 A1
- Document ID: US20140157397A1
- Status: Published application
- Kind: A1
- Application number: 13/900,359
- Filed: 2013-05-22
- Published: 2014-06-05
- Earliest claimed: 2012-05-22
- Assignees: Xockets, Inc.
- Applicants: Xockets IP, LLC
- Inventors: Parin Bhadrik Dalal; Stephen Paul Belair
- Web page: https://patentgrep.com/patent/US20140157397A1

## CPC

- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1652: {in a multiprocessor architecture (interprocessor communication using common memory G06F15/167)}
- G06F 13/1673: {using buffers}
- G06F 13/28: using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence)
- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/404: {with address mapping}
- G06F 13/4234: {being a memory bus}
- G06F 21/55: Detecting local intrusion or implementing counter-measures
- H04L 47/10: Flow control; Congestion control
- H04L 47/2441: relying on flow classification, e.g. using integrated services [IntServ]
- H04L 49/70: {Virtual switches}
- H04L 63/0227: {Filtering policies (mail message filtering H04L51/212)}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A packet handling system is disclosed that can include at least one main processor, a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor; an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

## Claims

### Claim 1

A packet handling system, comprising:
at least one main processor,
a plurality of offload processors connected to a memory bus and configured to provide security related services on packets prior to redirection to the main processor;
an arbiter connected to each of the plurality of offload processors, the arbiter capable of scheduling resource priority for instructions or data received from the memory bus; and
a virtual switch respectively connected to the main processor and the plurality of offload processors using the memory bus, with the virtual switch capable of receiving memory read/write data over the memory bus, and further directing at least some memory read/write data to the arbiter.

### Claim 2 (depends on 1)

The packet handling system of claim 1, wherein the offload processors provide support for signature detection by an intrusion prevention system.

### Claim 3 (depends on 1)

The packet handling system of claim 1, wherein the offload processors provide support for encryption/decryption.

### Claim 4 (depends on 1)

The packet handling system of claim 1, further comprising a network interface card with single root IO virtualization (SR-IOV), to receive the packets and direct packets to one of the offload processors acting as a virtual switch, with packets being passed to the offload processor by the virtual switch and an input-out memory management unit (IOMMU).

### Claim 5 (depends on 1)

The packet handling system of claim 1, wherein the offload processors are connected to memory, and further include a snoop control unit for coherent read out and write in to memory.

### Claim 6 (depends on 1)

The packet handling system of claim 1, wherein the offload processors are connected to memory to permit zero-overhead context switching between threads of a networked application.

### Claim 7 (depends on 1)

The packet handling system of claim 1, wherein the offload processors are connected to memory and a computational FPGA, all being mounted together on XIMM module configured for insertion into a DIMM socket.