# US 2014/0157220 A1 · Layout design apparatus and layout design method

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- Number: US 2014/0157220 A1
- Document ID: US20140157220A1
- Status: Published application
- Kind: A1
- Application number: 14/175,000
- Filed: 2014-02-07
- Published: 2014-06-05
- Earliest claimed: 2011-08-04
- Assignees: Fujitsu Limited
- Inventors: Masashi Arayama; Yuuki Watanabe
- Web page: https://patentgrep.com/patent/US20140157220A1

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A layout design apparatus includes: a memory unit to store design data of a hierarchical layout of a multilayer circuit including a macro; a channel count calculation unit to calculate a channel count of channels available to lead wiring from a terminal of the macro to a wiring layer based on the design data stored in the memory unit; and a path calculation unit to calculate a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

## Claims

### Claim 1

(canceled)

### Claim 2

(canceled)

### Claim 3

(canceled)

### Claim 4

(canceled)

### Claim 5

(canceled)

### Claim 6

(canceled)

### Claim 7

A layout design method, comprising:
executing by a computer operations of:
calculating a channel count of channels available to lead wiring from a terminal of a macro to a wiring layer based on design data of a hierarchical layout of a multilayer circuit including the macro; and
sequentially calculating a path for leading wiring from a terminal of the macro to the wiring layer in ascending order of the channel count.

### Claim 8 (depends on 7)

The layout design method according to claim 7, further comprising,
determining whether or not a leading path is calculated for all terminals of the macro.

### Claim 9 (depends on 7)

The layout design method according to claim 7, further comprising:
storing information regarding leading paths in the memory unit when the leading path is calculated for all terminals of the macro; and
designing leading wiring for each terminal of the macro based on the information.

### Claim 10 (depends on 7)

The layout design method according to claim 7, further comprising:
calculating a reduction ratio of the channel count for channels available to lead wiring to the wiring layer due to effects from leading wiring of other terminals; and
calculating the path based on a first terminal which reduction ratio is larger than a threshold value and a second terminal that affects the reduction in the channel count of the first terminal.

### Claim 11 (depends on 7)

The layout design method according to claim 7, further comprising, going back to a path calculation of a previous terminal before the terminal whose path is not calculated.

### Claim 12 (depends on 7)

The layout design method according to claim 7, further comprising, performing the path calculation until a new path other than a calculated path is obtained.

### Claim 13

(canceled)

### Claim 14

(canceled)

### Claim 15

(canceled)

### Claim 16

(canceled)

### Claim 17

(canceled)

### Claim 18

(canceled)