# US 2014/0157213 A1 · Method of generating a set of defect candidates for wafer

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- Number: US 2014/0157213 A1
- Document ID: US20140157213A1
- Status: Published application
- Kind: A1
- Application number: 13/692,396
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, L
- Inventors: Min-Hsin HSIEH; Tsung-Hsien LEE
- Web page: https://patentgrep.com/patent/US20140157213A1

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G03F 1/36: Masks having proximity correction features; Preparation thereof, e.g. optical proximity correction [OPC] design processes
- G03F 1/86: by charged particle beam [CPB]
- G03F 7/705: {Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions}
- G03F 7/7065: {Defects, e.g. optical inspection of patterned layer for defects}
- G06F 30/30: Circuit design
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 2115/08: Intellectual property [IP] blocks or IP cores
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

A method of generating a set of defect candidates for a wafer includes generating a filtration area according to a graph operation of one or more of a plurality of layout areas. The wafer includes at least one die manufactured according to a mask, and the mask is prepared by combining the plurality of layout areas. The method further includes generating the set of defect candidates by omitting a subset of initial defect candidates having positions within the filtration area.

## Claims

### Claim 1

A method of generating a set of defect candidates for a wafer, the wafer comprising at least one die manufactured according to a mask, the mask being prepared by combining a plurality of layout areas, the method comprising:
generating, by a hardware processor, a filtration area according to a graph operation of one or more of the plurality of layout areas; and
generating the set of defect candidates having positions outside the filtration area,
wherein the plurality of layout areas comprises a layout area including a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of layout areas comprises a first layout area and a second layout area, a first peripheral edge of the first layout area arranged to be adjacent to a first peripheral edge of the second layout area on the mask, and the graph operation comprises:
expanding the first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance; and
generating the filtration area by subtracting the first layout area from the expanded first layout area.

### Claim 3 (depends on 2)

The method of claim 2, wherein the first predetermined distance ranges from 0.5 μm to 1.0 μm.

### Claim 4 (depends on 2)

The method of claim 2, wherein the first layout area has a second peripheral edge arranged to be adjacent to a second peripheral edge of the second layout area on the mask, and the expansion of the first layout area further comprises:
expanding the first layout area by shifting the second peripheral edge of the first layout area outwardly by a second predetermined distance.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second predetermined distance ranges from 0.5 μm to 1.0 μm.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plurality of layout areas comprises a first layout area and a second layout area, a first peripheral edge of the first layout area arranged to be adjacent to a first peripheral edge of the second layout area on the mask, and the graph operation comprises:
expanding the first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance;
shrinking the first layout area by shifting the first peripheral edge of the first layout area inwardly by a second predetermined distance; and
generating the filtration area by subtracting the shrunk first layout area from the expanded first layout area.

### Claim 7 (depends on 1)

The method of claim 1, wherein the graph operation comprises:
generating a non-filtration area according to the plurality of layout areas; and
generating the filtration area by subtracting the non-filtration area from a full area encompassing all the plurality of layout areas.

### Claim 8 (depends on 7)

The method of claim 7, wherein the generation of the non-filtration area comprises:
generating the non-filtration area by adding one or more of the plurality of layout areas.

### Claim 9 (depends on 7)

The method of claim 7, wherein the plurality of layout areas comprises a first layout area and a second layout area, a first peripheral edge of the first layout area arranged to be adjacent to a first peripheral edge of the second layout area on the mask, and the generation of the non-filtration area comprises:
adjusting the first layout area by shifting the first peripheral edge of the first layout area by a first predetermined distance; and
generating the non-filtration area including the adjusted first layout area.

### Claim 10 (depends on 9)

The method of claim 9, wherein the first layout area has a second peripheral edge arranged to be adjacent to a second peripheral edge of the second layout area on the mask, and the expansion of the first layout area further comprises:
adjusting the first layout area by shifting the second peripheral edge of the first layout area by a second predetermined distance.

### Claim 11 (depends on 1)

The method of claim 1, wherein the generation of the filtration area comprises:
receiving filtration area information compiled in a graphic data format recognizable by a layout software program.

### Claim 12

(canceled)

### Claim 13

A non-transitory computer readable storage medium encoded with a computer program code, the computer program code being arranged to cause a hardware processor to:
generate a filtration area for a wafer manufactured based on a mask, the mask including a plurality of layout areas; and
generate a set of filtered defect candidates by filtering out a subset of initial defect candidates located within the filtration area,
wherein the plurality of layout areas comprises a layout area including a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.

### Claim 14 (depends on 13)

The non-transitory computer readable storage medium of claim 13, wherein the plurality of layout areas comprises a first layout area and a second layout area, a first peripheral edge of the first layout area being arranged to be adjacent to a first peripheral edge of the second layout area on a mask, and the generation of the filtration area comprises:
generating an expanded first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance; and
generating the filtration area by subtracting the first layout area from the expanded first layout area.

### Claim 15 (depends on 13)

The non-transitory computer readable storage medium of claim 13, wherein the generation of the filtration area comprises:
generating a non-filtration area according to the plurality of layout areas; and
generating the filtration area by subtracting the non-filtration area from a full area encompassing all the plurality of layout areas.

### Claim 16 (depends on 15)

The non-transitory computer readable storage medium of claim 15, wherein the generation of the non-filtration area comprises:
generating the non-filtration area by adding one or more of the plurality of layout areas.

### Claim 17 (depends on 13)

The non-transitory computer readable storage medium of claim 13, wherein the generation of the filtration area comprises:
causing the hardware processor to receive filtration area information compiled in a graphic data format recognizable by a layout software program.

### Claim 18

A method of generating a boundary area between a first layout area and a second layout area of a mask, a first peripheral edge of the first layout area being arranged to be adjacent to the second layout area on the mask, the method comprising:
expanding, by a hardware processor, the first layout area by shifting the first peripheral edge of the first layout area outwardly by a first predetermined distance; and
generating the boundary area by subtracting the first layout area from the expanded first layout area,
wherein the first layout area or the second layout area comprises a layout design of a digital circuit clock, an analog circuit block, a memory circuit block, a power-device circuit block, or an intellectual property (IP) circuit block.

### Claim 19 (depends on 18)

The method of claim 18, wherein the first predetermined distance ranges from 0.5 μm to 1.0 μm.

### Claim 20 (depends on 18)

The method of claim 18, wherein a second peripheral edge of the first layout area is arranged to be adjacent to the second layout area on the mask, and the method further comprises:
expanding the first layout area by shifting the second peripheral edge of the first layout area outwardly by a second predetermined distance.

### Claim 21 (depends on 20)

The method of claim 20, wherein the second predetermined distance ranges from 0.5 μm to 1.0 μm.

### Claim 22 (depends on 18)

The method of claim 18, further comprising:
compiling the boundary area in a graphic data format recognizable by a layout software program.