# US 2014/0157212 A1 · Distinguishable IC Patterns with Encoded Information > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157212 A1 - Document ID: US20140157212A1 - Status: Published application - Kind: A1 - Application number: 13/692,845 - Filed: 2012-12-03 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, L - Inventors: Shih-Ming Chang; Tzu-Chin Lin; Jen-Chieh Lo; Yu-Po Tang; Tsong-Hua Ou - Web page: https://patentgrep.com/patent/US20140157212A1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - G06F 2119/18: Manufacturability analysis or optimisation for manufacturability - H10D 89/10: Integrated device layouts - H10W 46/301: {for alignment} - H10W 46/401: {for identification or tracking} - H10W 46/501: {for use before dicing} - Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS] - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS ## Abstract A method of designing an IC design layout having similar patterns filled with a plurality of indistinguishable dummy features, in a way to distinguish all the patterns, and an IC design layout so designed. To distinguish each pattern in the layout, deviations in size and/or position from some predetermined equilibrium values are encoded into a set of selected dummy features in each pattern at the time of creating dummy features during the design stage. By identifying such encoded dummy features and measuring the deviations from image information provided by, for example, a SEM picture of a wafer or photomask, the corresponding pattern can be located in the IC layout. For quicker and easier identification of the encoded dummy features from a given pattern, a set of predetermined anchor dummy features may be used. ## Claims ### Claim 1 A method of making an integrated circuit (“IC”) design layout in a way to distinguish a plurality of similar patterns contained therein, each of the patterns comprising a plurality of dummy features, the method comprising: identifying an anchor group of anchor dummy features as a subset of the plurality of dummy features in each of the patterns, the anchor group being present in each of the patterns and having identical configuration, size, and location thereof; identifying at least one tunable dummy feature as a subset of the plurality of dummy features in each of the patterns, the at least one tunable dummy feature having a fixed spatial relationship with the anchor group of the respective pattern; determining tuning parameters to be varied for having the at least one tunable dummy feature deviated; determining, for each tuning parameter, deviation values by which the tuning parameter can be varied; and using a computer, varying the at least one tunable dummy feature in each of the patterns by at least one of the deviation values in such a way that different patterns become distinguishable from one another through the tunable dummy features so varied. ### Claim 2 (depends on 1) The method of claim 1, wherein the tuning parameters are selected from a group consisting of a width, a height, an x-pitch, a y-pitch, or a shape of each tunable dummy feature. ### Claim 3 (depends on 2) The method of claim 2, wherein for each tuning parameter, the deviation values are discrete numbers of a constant interval. ### Claim 4 (depends on 1) The method of claim 1, wherein the deviation values are determined in consideration of a resolution of a picture from an inspection tool such that the magnitude of deviation of each tunable dummy feature can be discernible from the picture. ### Claim 5 (depends on 1) The method of claim 1, wherein identifying the at least one tunable dummy feature includes: determining the number of the tunable dummy features common to all the patterns, and determining positions of the tunable dummy features common to all the patterns. ### Claim 6 (depends on 5) The method of claim 5, wherein the number of the tunable dummy features is determined in consideration of the number of patterns to be distinguished in the IC design layout. ### Claim 7 (depends on 1) The method of claim 1, further comprising determining equilibrium values to be respectively assigned to the tuning parameters of each tunable dummy feature. ### Claim 8 (depends on 1) The method of claim 1, wherein identifying the anchor group of anchor dummy features includes: determining the number of the anchor dummy features common to all the patterns, determining positions of the anchor dummy features common to all the pattern, and determining anchor parameters and anchor values to be respectively assigned thereto for each anchor dummy feature. ### Claim 9 (depends on 8) The method of claim 8, wherein, within each of the patterns, the anchor dummy features share a common set of the anchor parameters and the anchor values. ### Claim 10 (depends on 8) The method of claim 8, wherein in all the patterns, the anchor dummy features share a common set of the anchor parameters and the anchor values. ### Claim 11 An integrated circuit (IC) layout comprising a plurality of resembling patterns, each of the patterns comprising, a plurality of dummy features arrayed in a substantially regular fashion, each dummy feature having an identical set of observable parameters, each observable parameter having a numerical value, the plurality of dummy features comprising: an anchor group of anchor dummy features, wherein in all the patterns, any two correspondingly situated anchor dummy features share a common set of the numerical values with respect to the observable parameters thereof; and one or more tunable dummy features, each of the tunable dummy features having a fixed predetermined spatial relationship with the anchor group of anchor dummy features, wherein the tunable dummy features in each of the patterns have unique sets of the numerical values with respect to the observable parameters thereof such that any two of the patterns can be distinguished by their respective tunable dummy features. ### Claim 12 (depends on 11) The IC layout of claim 11, wherein the observable parameters for each dummy feature are chosen from a group consisting of a width, a height, an x-pitch, a y-pitch, and a shape of the respective dummy feature. ### Claim 13 (depends on 11) The IC layout of claim 11, wherein the numerical value for each observable parameter of the tunable dummy features is chosen from a set of discrete numbers of an equal interval. ### Claim 14 (depends on 13) The IC layout of claim 13, wherein the constant interval is equal to a minimum dimension that a picture from an inspection tool of a given resolution is capable of resolving. ### Claim 15 (depends on 11) The IC layout of claim 11, wherein all the anchor dummy features within each pattern share a common set of the numerical values assigned to the respective observable parameters ### Claim 16 (depends on 11) The IC layout of claim 11, wherein in all the patterns, the respective anchor groups have identical number of the anchor dummy features, identical configuration, and identical location in the respective patterns. ### Claim 17 A method comprising: receiving an integrated circuit design layout in a computer-readable medium, wherein the integrated circuit design layout includes a plurality of patterns, each of the patterns includes an anchor group of dummy features and a set of at least one tunable dummy feature that has a fixed predetermined spatial relationship with the anchor group, the anchor group of each of the patterns has a predetermined configuration, size, and location thereof, the anchor group is identical in each of the patterns, and the set of at least one tunable dummy feature is different in each of the patterns; receiving image information of a first pattern to be located in the IC design layout; determining, from the image information, a first anchor group of dummy features of the first pattern based on the predetermined configuration, size, and location; determining, from the image information, a first set of at least one tunable dummy feature of the first pattern based on the fixed predetermined spatial relationship with the first anchor group; and using a computer, locating one of the plurality of patterns in the integrated circuit design layout by matching the set of at least one tunable dummy feature of the one of the plurality of patterns to the first set. ### Claim 18 (depends on 17) The method of claim 17, further comprising, before the locating one of the plurality of patterns: determining, from the image information, magnitudes of deviation in size and position by which each of the first set is deviated from a predetermined equilibrium size and position, wherein the matching uses the magnitudes of deviation. ### Claim 19 (depends on 18) The method of claim 18, wherein the deviation in size includes deviation in width, height, or both. ### Claim 20 (depends on 18) The method of claim 18, wherein the deviation in position includes deviation in x-pitch, y pitch, or both.