# US 2014/0157085 A1 · Redundant data storage schemes for multi-die memory systems

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- Number: US 2014/0157085 A1
- Document ID: US20140157085A1
- Status: Published application
- Kind: A1
- Application number: 14/173,245
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2010-01-11
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Ofir Shalvi; Naftali Sommer; Uri Perlmutter; Julian Vlaiko; Moshe Neerman
- Web page: https://patentgrep.com/patent/US20140157085A1

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G06F 11/14: Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16)
- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 12/023: {Free address space management}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

## Claims

### Claim 1

An apparatus, comprising:
a first memory device, wherein the first memory device includes a first plurality of blocks;
a second memory device, wherein the second memory device includes a second plurality of blocks; and
a controller coupled to the first memory device and the second memory device, wherein the controller is configured to:
read data stored in a first block of the first plurality of blocks;
store the read data in a second block of the second plurality of blocks;
check the data stored in the second block of the second plurality of blocks; and
re-read the data stored in the first block of the first plurality of blocks responsive to a determination that the data stored in the second block of the second plurality of blocks includes at least one error.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein each block of the first plurality of blocks and the second plurality of blocks includes a respective plurality of non-volatile memory cells.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the data stored in the first block of the plurality of blocks is encoded with an Error Correction Code.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein to store the read data in the second block of the second plurality of blocks, the controller is further configured to erase the data stored in the first block of the first plurality of blocks responsive to a determination that the first block in the first plurality of blocks is needed to store new data.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein to store the read data in the second block of the second plurality of blocks, the controller is further configured to erase the data stored in the first block of the first plurality of blocks after a time period has elapsed since the read data has been stored in the second memory block of the second plurality of blocks.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein to re-read the data stored in the first block of the first plurality of blocks, the controller is further configured to determine if the data stored in the first block of the first plurality of blocks has been erased.

### Claim 7

A method, comprising:
reading data stored in a first block in a first memory die;
storing the read data in a second block in a second memory die, wherein the second memory die is different than the first memory die;
checking the data stored in the second block in the second memory die; and
re-reading the data stored in the first block in the first memory die responsive to a determination that the data stored in the second block in the second memory die includes at least one error.

### Claim 8 (depends on 7)

The method of claim 7, wherein storing the read data in the second block in the second memory die comprises erasing the data stored in the first block in the first memory die after a time period has elapsed since the storing of the read data in the second memory block.

### Claim 9 (depends on 7)

The method of claim 7, wherein re-reading the data stored in the first block in the first memory comprises determining if the data stored in the first block in the memory has been erased.

### Claim 10 (depends on 7)

The method of claim 7, wherein the data stored in the first block in the first memory die is encoded with an Error Correction Code.

### Claim 11 (depends on 7)

The method of claim 7, wherein storing the read data in the second block in the second memory die comprises erasing the data stored in the first block in the first memory die responsive to a determination that the first block in the first memory die is needed to stored new data.

### Claim 12 (depends on 7)

The method of claim 7, wherein the first memory block includes a first plurality of memory cells and the second memory block includes a second plurality of memory cells, and wherein each memory cell of the first plurality of memory cells and the second plurality of memory cells comprises a multi-level non-volatile storage cell.

### Claim 13 (depends on 7)

The method of claim 7, wherein the first memory die comprises a non-volatile memory, and wherein the second memory die comprises non-volatile memory.

### Claim 14

A system, comprising:
a host processor; and
a storage unit coupled to the host processor, wherein the storage unit includes a first memory device and a second memory device, and wherein the
storage unit is configured to:
read data stored in a first block of the first memory device;
store the read data in a second block of the second memory device;
check the data stored in the second block of the second memory device; and
re-read the data stored in the first block of the first memory device responsive to a determination that the data stored in the second block of the second memory device includes at least one error.

### Claim 15 (depends on 14)

The system of claim 14, wherein to store the read data in the second block of the second memory device, the storage unit is further configured to erase the data stored in the first block of the first memory device after a time period has elapsed since the read data has been stored in the second memory block of the second memory device.

### Claim 16 (depends on 14)

The system of claim 14, wherein to re-read the data stored in the first block of the first memory device, the storage unit is further configured to determine if the data stored in the first block of the first memory device has been erased.

### Claim 17 (depends on 14)

The system of claim 14, wherein the data stored in the first block of the first memory device is encoded with an Error Correction Code.

### Claim 18 (depends on 14)

The system of claim 14, wherein to store the read data in the second block of the second memory device, the storage unit is further configured to erase the data stored in the first block of the first memory device responsive to a determination that the first block in the first memory device is needed to store new data.

### Claim 19 (depends on 14)

The system of claim 14, wherein the first memory block includes a first plurality of memory cells and the second memory block includes a second plurality of memory cells, and wherein each memory cell of the first plurality of memory cells and the second plurality of memory cells comprises a multi-level non-volatile storage cell.

### Claim 20 (depends on 14)

The system of claim 14, wherein the first memory device comprises a non-volatile memory, and wherein the second memory device comprises non-volatile memory.