# US 2014/0157084 A1 · Distortion estimation and cancellation in memory devices

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- Number: US 2014/0157084 A1
- Document ID: US20140157084A1
- Status: Published application
- Kind: A1
- Application number: 14/090,431
- Filed: 2013-11-26
- Published: 2014-06-05
- Earliest claimed: 2006-05-12
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Ofir Shalvi; Naftali Sommer; Eyal Gurgi; Ariel Maislos
- Web page: https://patentgrep.com/patent/US20140157084A1

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for operating a memory (28) includes storing data in a group of analog memory cells (32) of the memory as respective first voltage levels. After storing the data, second voltage levels are read from the respective analog memory cells. The second voltage levels are affected by cross-coupling interference causing the second voltage levels to differ from the respective first voltage levels. Cross-coupling coefficients, which quantify the cross-coupling interference among the analog memory cells, are estimated by processing the second voltage levels. The data stored in the group of analog memory cells is reconstructed from the read second voltage levels using the estimated cross-coupling coefficients.

## Claims

### Claim 1

An apparatus, comprising:
an interface configured to communication with a memory, wherein the memory includes a plurality of memory cells; and
a processor coupled to the interface, wherein the processor is configured to:
read one or more values from a respective one or more memory cells of a subset of the plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimate distortion levels in the read one or more values;
read another value from another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predict a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjust the read value from the another memory cell dependent upon the predicted distortion level; and
reconstruct the data stored in the another memory cells dependent upon the adjusted read value from the another memory cell.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein to predict the distortion level in the read another value, the processor is further configured to compare a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein to predict the distortion level in the read another value, the processor is further configured to:
track one or more parameters common to the subset of the plurality of memory cells; and
store the tracked one or more parameters in a data structure.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.

### Claim 7

A method for operating a memory, the method comprising:
reading one or more values from a respective one or more memory cells of a subset of a plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimating distortion levels in the read one or more values;
reading another value from another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predicting a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjusting the read value from the another memory cell dependent upon the predicted distortion level; and
reconstructing the data stored in the another memory cells dependent upon the adjusted read value from the another memory cell.

### Claim 8 (depends on 7)

The method of claim 7, wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).

### Claim 9 (depends on 7)

The method of claim 7, wherein predicting the distortion level in the read another value comprises comparing a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.

### Claim 10 (depends on 7)

The method of claim 7, wherein predicting the distortion level in the read another value comprises:
tracking one or more parameters common to the subset of the plurality of memory cells; and
storing the tracked one or more parameters in a data structure.

### Claim 11 (depends on 7)

The method of claim 7, wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.

### Claim 12 (depends on 7)

The method of claim 7, wherein each memory cell of the subset of the plurality of memory cells is coupled to common circuitry.

### Claim 13 (depends on 7)

The method of claim 7, wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.

### Claim 14

A system, comprising:
a memory including a plurality of memory cells; and
a controller coupled to the memory, wherein the controller is configured to:
read one or more values from a respective one or more memory cells of a subset of the plurality of memory cells of the memory, wherein the read values correspond to data stored in the one or more memory cells;
estimate distortion levels in the read one or more values;
read another value from another memory cell of the subset of the plurality of memory cells, wherein the read another value corresponds to data stored in the another memory cell;
predict a distortion level in the read another value dependent upon the estimated distortion levels in the read one or more values;
adjust the read value from the another memory cell dependent upon the predicted distortion level; and
reconstruct the data stored in the another memory cells dependent upon the adjusted read value from the another memory cell.

### Claim 15 (depends on 14)

The system of claim 14, wherein the data stored in the another memory cell is encoded with an Error Correction Code (ECC).

### Claim 16 (depends on 14)

The system of claim 14, wherein to predict the distortion level in the read another value, the controller is further configured to compare a value of a parameter relating to the another memory cell measured at a time when the another memory cell was programmed to a value of the parameter relating to the memory cell measured at a time when the another memory cell was read.

### Claim 17 (depends on 14)

The system of claim 14, wherein to predict the distortion level in the read another value, the controller is further configured to:
track one or more parameters common to the subset of the plurality of memory cells; and
store the tracked one or more parameters in a data structure.

### Claim 18 (depends on 14)

The system of claim 14, wherein each memory cell of the subset of the plurality of memory cells is coupled to a common bit line.

### Claim 19 (depends on 14)

The system of claim 14, wherein each memory cell of the subset of the plurality of memory cells is coupled to a common word line.

### Claim 20 (depends on 14)

The system of claim 14, wherein each memory cell of the plurality of memory cells comprises a non-volatile memory cell.