# US 2014/0157083 A1 · Redundant data storage schemes for multi-die memory systems

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- Number: US 2014/0157083 A1
- Document ID: US20140157083A1
- Status: Published application
- Kind: A1
- Application number: 14/173,271
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 2010-01-11
- Assignees: Apple Inc.
- Applicants: Apple Inc.
- Inventors: Ofir Shalvi; Naftali Sommer; Uri Perlmutter; Julian Vlaiko; Moshe Neerman
- Web page: https://patentgrep.com/patent/US20140157083A1

## CPC

- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 3/065: {Replication mechanisms}
- G06F 3/0655: {Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices}
- G06F 3/0688: {Non-volatile semiconductor memory arrays}
- G06F 11/1016: {Error in accessing a memory location, i.e. addressing error}
- G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD}
- G06F 11/14: Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16)
- G06F 11/1666: {where the redundant component is memory or memory area}
- G06F 12/023: {Free address space management}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F 2212/7205: Cleaning, compaction, garbage collection, erase control
- G06F 2212/7208: Multiple device management, e.g. distributing data over multiple flash devices
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

## Claims

### Claim 1

A method for data storage, comprising:
in a memory that includes at least N memory units, defining a mapping between logical addresses and respective physical storage locations in the memory units;
selecting a set of N logical addresses, which are mapped to N respective physical storage locations in different ones of the memory units, such that K of the logical addresses in the set, 1≦K<N, are assigned for data storage and N−K logical addresses in the set, other than the K logical addresses, are assigned for storing redundancy information;
accepting data for storage in the K logical addresses in the set;
computing the redundancy information for the data;
storing the data in the K logical addresses at a first storage density; and
storing the redundancy information in the N−K logical addresses at a second density that is lower than the first storage density.

### Claim 2 (depends on 1)

The method according to claim 1, and comprising selecting an additional set of the logical addresses for storing additional data and additional redundancy information, such that the logical addresses that are assigned for storing the additional redundancy information in the additional set are mapped to a different subset of the memory units, in comparison with the logical addresses that are assigned for storing the redundancy information in the set.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the memory units are assigned respective, non-overlapping ranges of the logical addresses, and wherein selecting the set comprises choosing the N logical addresses from the respective ranges.

### Claim 4 (depends on 1)

The method according to claim 1, wherein accepting the data comprises receiving the data from a host, and wherein selecting the set comprises assigning the N−K logical addresses from a range of the logical addresses that is not accessible to the host.

### Claim 5 (depends on 1)

The method according to claim 1, and comprising reserving at least one spare memory unit in addition to the N memory units, and replacing a failed memory unit from among the N memory units with the spare memory unit.

### Claim 6 (depends on 5)

The method according to claim 5, and comprising temporarily using the spare memory unit for improving performance of data storage in the N memory units.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the memory units are partitioned into multiple groups that are associated with respective multiple processors, and wherein storing the data and the redundancy information comprises distributing storage of the data and the redundancy information among the multiple processors.

### Claim 8

A data storage apparatus, comprising:
an interface, which is configured to communicate with a memory that includes at least N memory units; and
a processor, which is configured to define a mapping between logical addresses and respective physical storage locations in the memory units, to select a set of N logical addresses, which are mapped to N respective physical storage locations in different ones of the memory units, such that K of the logical addresses in the set, 1≧K<N, are assigned for data storage and N−K logical addresses in the set, other than the K logical addresses, accept data for storage in the K logical addresses in the set, to compute the redundancy information for the data to store the data in the K logical addresses at a first storage density, and to store the redundancy information in the N−K logical addresses at a second storage density that is lower than the first storage density.

### Claim 9 (depends on 8)

The apparatus according to claim 8, wherein the memory units are assigned respective, non-overlapping ranges of the logical addresses, and wherein the processor is configured to select the N logical addresses from the respective ranges.

### Claim 10 (depends on 8)

The apparatus according to claim 8, wherein the interface is configured to receive the data from a host, and wherein the processor is configured to assigned the N−K logical addresses from a range of the logical addresses that is not accessible to the host.

### Claim 11 (depends on 1)

The apparatus according to claim 1, wherein the processor is configured to reserve at least one spare memory unit in addition to the N memory units, and to replace a failed memory unit from among the N memory units with the spare memory unit.

### Claim 12 (depends on 11)

The apparatus according to claim 11, wherein the processor is configured to temporarily use the spare memory unit for improving performance of data storage in the N memory units.

### Claim 13 (depends on 1)

The apparatus according to claim 1, wherein the memory units are partitioned into multiple groups that are associated with respective multiple processors, and wherein the processor is configured to distribute storage of the data and the redundancy information among the multiple processors.