# US 2014/0157078 A1 · Methods, solid state drive controllers and data storage devices having a runtime variable raid protection scheme > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157078 A1 - Document ID: US20140157078A1 - Status: Published application - Kind: A1 - Application number: 13/756,328 - Filed: 2013-01-31 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: Western Digital Technologies, Inc. - Inventors: RADOSLAV DANILAK; RODNEY N. MULLENDORE; JUSTIN JONES; ANDREW J. TOMLIN - Web page: https://patentgrep.com/patent/US20140157078A1 ## CPC - H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit - G06F 11/1012: {using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence)} - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G06F 11/108: {Parity data distribution in semiconductor storages, e.g. in SSD} - G06F 16/1847: {specifically adapted to static storage, e.g. adapted to flash memory or SSD} - H03M 13/1102: {Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes} - H03M 13/1515: {Reed-Solomon codes} - H03M 13/353: {Adaptation to the channel} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data storage device may comprise a flash controller and an array of flash memory devices coupled to the flash controller. The array may comprise a plurality of S-Pages that may each comprise a plurality of F-Pages. In turn, each of the plurality of F-Pages may be configured to store a variable amount of data and a variable amount of error correction code. The flash controller may be configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within one or more F-Pages having the largest amount of data. ## Claims ### Claim 1 A solid state drive controller, comprising: a processor, the processor being configured to couple to an array of flash memory devices, the array comprising a plurality of dies, each die comprising a plurality of flash blocks (F-Blocks), each F-Block comprising a plurality of flash pages (F-Pages), at least some of the F-Page comprising at least one error correcting code page (E-Page), and at least some of the E-Pages comprising a variably-sized error correction code (ECC) portion and a corresponding variably-sized data portion, the variably-sized data portions within one F-Page defining, in the aggregate, an F-Page data portion, wherein the processor is configured to: define an S-Page that comprises a plurality of F-Pages from one or more of the plurality of dies; within the S-Page, store an E-Page error correction code within the variably-sized ECC portion of each E-Page within the F-Pages to correct an error within the corresponding variably-sized data portion; designate at least one F-Page having a largest size F-Page data portion among the F-Pages in the S-Page as a Check Page; and store a cross-F-Page error correction code within the at least one Check Page. ### Claim 2 (depends on 1) The solid state drive controller of claim 1, wherein the cross-F-Page error correction code comprises a Forward Error Correction (FEC) code. ### Claim 3 (depends on 2) The solid state drive controller of claim 2, wherein the FEC code comprises a Reed-Solomon code. ### Claim 4 (depends on 1) The solid state drive controller of claim 1, wherein the E-Page error correction code comprises a Low-Density Parity-Check (LDPC) error correction code. ### Claim 5 (depends on 1) The solid state drive controller of claim 1, wherein the processor is configured to generate and store the E-Page error correction code at runtime, at a time of generating one of the plurality of E-Pages. ### Claim 6 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to generate the cross-F-Page error correction code for the S-Page as data is written to the S-Page. ### Claim 7 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to read data from the S-Page and to skip the at least one F-Page within the S-Page that has been designated as a Check Page. ### Claim 8 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to: set a flag in a block information data structure to designate particular F-Pages within an S-Page as being Check Pages; and consult the block information data structure to determine which of the F-Pages of an S-Page have been designated as Check Pages. ### Claim 9 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to designate additional F-Pages in the S-Page as Check Pages, depending upon at least one of: (1) a configuration of the array, (2) a performance of the array and (3) a use-profile of predetermined portions of the array. ### Claim 10 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to designate additional F-Pages as Check Pages in S-Pages storing a predetermined type of information. ### Claim 11 (depends on 10) The solid state drive controller of claim 10, wherein the predetermined type of information comprises metadata. ### Claim 12 (depends on 10) The solid state drive controller of claim 10, wherein the predetermined type of information comprises host-indicated data. ### Claim 13 (depends on 1) The solid state drive controller of claim 1, wherein as between a first S-Page and a second S-Page, the at least one F-Page designated as a Check Page in the first S-Page occupies a comparatively different position within the first S-Page as does the at least one F-Page designated as a Check Page within the second S-Page. ### Claim 14 (depends on 1) The solid state drive controller of claim 1, wherein the S-Page is a first S-Page and the controller is further configured to define a second S-Page that has a greater number of F-Pages designated as Check Pages than the first S-Page. ### Claim 15 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to, when writing to an F-Block, determine at least one of: (1) a strength of E-Page error correction code to generate within the variably-sized ECC portion of each E-Page; (2) a strength of cross-F-Page error correction code to generate; and (3) which F-Pages within an S-Page to designate as a Check Page. ### Claim 16 (depends on 1) The solid state drive controller of claim 1, wherein the processor is further configured to apply the cross-F-Page error correction code when the E-Page error correction code fails to correct an encountered error. ### Claim 17 (depends on 1) A data storage device, comprising: the controller of claim 1, and the array of flash memory devices. ### Claim 18 A method of controlling a data storage device, the data storage device comprising a processor, the processor being configured to couple to an array of flash memory devices, the array comprising a plurality of dies, each die comprising a plurality of flash blocks (F-Blocks), each F-Block comprising a plurality of flash pages (F-Pages), at least some of the F-Page comprising at least one error correcting code page (E-Page), and at least some of the E-Pages comprising a variably-sized error correction code (ECC) portion and a corresponding variably-sized data portion, the variably-sized data portions within one F-Page defining, in the aggregate, an F-Page data portion, the method comprising: defining an S-Page that comprises a plurality of F-Pages from one or more of the plurality of dies; within the S-Page, storing an E-Page error correction code within the variably-sized ECC portion of each E-Page within the F-Pages to correct an error within the corresponding variably-sized data portion; designating at least one F-Page having a largest size F-Page data portion among the F-Pages in the S-Page as a Check Page; and storing a cross-F-Page error correction code within the at least one Check Page. ### Claim 19 (depends on 18) The method of claim 18, wherein the cross-F-Page error correction code comprises a Forward Error Correction (FEC) code. ### Claim 20 (depends on 19) The method of claim 19, wherein the FEC code comprises a Reed-Solomon code. ### Claim 21 (depends on 18) The method of claim 18, wherein the E-Page error correction code comprises a Low-Density Parity-Check (LDPC) error correction code. ### Claim 22 (depends on 18) The method of claim 18, wherein storing the E-Page error correction code comprises generating and storing the E-Page error correction code at runtime, at a time of generating one of the plurality of E-Pages. ### Claim 23 (depends on 18) The method of claim 18, wherein storing the cross-F-Page error correction code comprises generating and storing the cross-F-Page error correction code for the S-Page as data is written to the S-Page. ### Claim 24 (depends on 18) The method of claim 18, further comprising reading data from the S-Page and skipping the at least one F-Page within the S-Page having been designated as a Check Page. ### Claim 25 (depends on 18) The method of claim 18, further comprising: setting a flag in a block information data structure to designate particular F-Pages within an S-Page as being Check Pages; and consulting the block information data structure to determine which of the F-Pages of an S-Page have been designated as Check Pages. ### Claim 26 (depends on 18) The method of claim 18, further comprising designating additional F-Pages in the S-Page as Check Pages, depending upon at least one of: (1) a configuration of the array, (2) a performance of the array and (3) a use-profile of predetermined portions of the array. ### Claim 27 (depends on 18) The method of claim 18, further comprising designating additional F-Pages as Check Pages in S-Pages storing a predetermined type of information. ### Claim 28 (depends on 27) The method of claim 27, wherein the predetermined type of information comprises one of metadata and host-indicated data. ### Claim 29 (depends on 18) The method of claim 18, wherein as between a first S-Page and a second S-Page, the at least one F-Page designated as a Check Page in the first S-Page occupies a comparatively different position within the first S-Page as does the at least one F-Page designated as a Check Page within the second S-Page. ### Claim 30 (depends on 18) The method of claim 18, wherein the S-Page is a first S-Page and wherein the method further comprises defining a second S-Page that has a greater number of F-Pages designated as Check Pages than the first S-Page. ### Claim 31 (depends on 18) The method of claim 18 wherein, when writing to an F-Block, the method further comprises determining at least one of: (1) a strength of E-Page error correction code to generate within the variably-sized ECC portion of each E-Page; (2) a strength of cross-F-Page error correction code to generate; and (3) which F-Pages within an S-Page to designate as a Check Page. ### Claim 32 (depends on 18) The method of claim 18, further comprising applying the cross-F-Page error correction code when the E-Page error correction code fails to correct an encountered error. ### Claim 33 A method of controlling a data storage device, the data storage device comprising a flash controller and an array of flash memory devices coupled to the flash controller, the array comprising a plurality of S-Pages that each comprise a plurality of F-Pages, the method comprising: storing, in each of the plurality of F-Pages, a variable amount of data and a variable amount of error correction code; generating an error correction code across each F-Page of an S-Page; and storing the generated error correction code within at least one F-Page having a largest amount of data. ### Claim 34 A solid state drive controller, comprising: a processor, the processor being configured to couple to an array of flash memory devices comprising a plurality of S-Pages that each comprise a plurality of F-Pages, each of the plurality of F-Pages being configured to store a variable amount of data and a variable amount of error correction code; wherein the processor is configured to generate an error correction code across each F-Page of an S-Page and to store the generated error correction code within at least one F-Page comprising a largest amount of data. ### Claim 35 (depends on 34) A data storage device, comprising: the controller of claim 34, and the array of flash memory devices.