# US 2014/0157074 A1 · Systems and Methods for Selective Retry Data Retention Processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157074 A1 - Document ID: US20140157074A1 - Status: Published application - Kind: A1 - Application number: 13/692,908 - Filed: 2012-12-03 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: LSI Corporation - Applicants: LSI Corporation - Inventors: Fan Zhang; Kaitlyn T. Nguyen; Jun Xiao - Web page: https://patentgrep.com/patent/US20140157074A1 ## CPC - G06F 11/0763: {by bit configuration check, e.g. of formats or tags} - G06F 11/0727: {in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097)} - H03M 13/1111: {Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms} - H03M 13/2957: {Turbo codes and decoding} - H03M 13/3723: {using means or methods for the initialisation of the decoder} - H03M 13/3738: {with judging correct decoding} - H03M 13/3746: {with iterative decoding} - H03M 13/3753: {using iteration stopping criteria} - H03M 13/6325: {Error control coding in combination with demodulation} - H03M 13/6343: {Error control coding in combination with techniques for partial response channels, e.g. recording} - G06F 11/1443: {Transmit or communication errors} - G11B 20/10527: {Audio or video recording; Data buffering arrangements (G11B20/12 - G11B20/18 take precedence)} - G11B 20/18: Error detection or correction; Testing {, e.g. of drop-outs} - H03M 13/1191: {Codes on graphs other than LDPC codes} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G11B: INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER (recording measured values in a way that does not require playback through a transducer G01D9/00; recording or playback apparatus using mechanically marked tape, e.g. punched paper tape, or using unit records, e.g. punched or magnetically marked cards G06K; transferring data from one type of record carrier to another G06K1/18; circuits for coupling output of reproducer to radio receiver H04B1/20; gramophone pick-ups or like acoustic electromechanical transducers or circuits therefor H04R) ## Abstract Systems, circuits, devices and/or methods related to systems and methods for data processing, and more particularly to systems and methods for re-processing data sets not successfully processed during standard processing. ## Claims ### Claim 1 A data processing system, the data processing system comprising: a data processing circuit operable to apply a data processing algorithm to a processing input to yield a data output; an input buffer operable to maintain at least a first data set and a second data set, wherein the first data set completed a first defined amount of processing by the data processing circuit without converging, and wherein the second data set is yet to complete a second defined amount of processing by the data processing circuit; a kick out circuit operable to compare an attribute of the second data set to a corresponding attribute of the first data set to determine whether the second data set will be maintained in the input buffer for additional processing after the second defined amount of processing by the data processing circuit; and wherein each of the first data set and the second data set are selectable as the processing input. ### Claim 2 (depends on 1) The data processing system of claim 1, wherein the first defined amount of processing by the data processing circuit is the same as the second defined amount of processing by the data processing circuit. ### Claim 3 (depends on 1) The data processing system of claim 1, wherein the attribute of the second data set is a number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is a number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit. ### Claim 4 (depends on 1) The data processing system of claim 1, wherein the data processing circuit comprises: a detector circuit operable to apply a data detection algorithm to the processing input to yield a detected output; and a decoder circuit operable to apply a data decode algorithm to a decoder input derived from the detected output to yield the data output. ### Claim 5 (depends on 4) The data processing system of claim 4, wherein the attribute of the second data set is a number of global iterations through both the data detector circuit and the data decoder circuit applied to the second data set during the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is a number of global iterations through both the data detector circuit and the data decoder circuit applied to the first data set during the first defined amount of processing by the data processing circuit. ### Claim 6 (depends on 4) The data processing system of claim 4, wherein the attribute of the second data set is a combination of a number of global iterations through both the data detector circuit and the data decoder circuit applied to the second data set during the second defined amount of processing by the data processing circuit and a number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is combination of a number of global iterations through both the data detector circuit and the data decoder circuit applied to the first data set during the first defined amount of processing by the data processing circuit and a number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit. ### Claim 7 (depends on 4) The data processing system of claim 4, wherein the detector circuit is selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit. ### Claim 8 (depends on 4) The data processing system of claim 4, wherein the decoder circuit is a low density parity check decoder circuit. ### Claim 9 (depends on 1) The data processing system of claim 1, wherein the system is implemented as an integrated circuit. ### Claim 10 (depends on 1) The data processing system of claim 1, wherein the data processing system is incorporated in a device selected from a group consisting of: a storage device, and a data transmission device. ### Claim 11 A method for data processing, the method comprising: providing a data processing circuit operable to apply a data processing algorithm to a processing input to yield a data output; providing an input buffer operable to maintain at least a first data set and a second data set, wherein the first data set completed a first defined amount of processing by the data processing circuit without converging, and wherein the second data set is yet to complete a second defined amount of processing by the data processing circuit; comparing an attribute of the second data set to a corresponding attribute of the first data set to determine whether the second data set will be maintained in the input buffer for additional processing after the second defined amount of processing by the data processing circuit; and selecting each of the first data set and the second data set as the processing input at respective times. ### Claim 12 (depends on 11) The method of claim 11, wherein the first defined amount of processing by the data processing circuit is the same as the second defined amount of processing by the data processing circuit. ### Claim 13 (depends on 11) The method of claim 11, wherein the attribute of the second data set is a number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is a number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit. ### Claim 14 (depends on 11) The method of claim 11, wherein the data processing circuit comprises: a detector circuit operable to apply a data detection algorithm to the processing input to yield a detected output; and a decoder circuit operable to apply a data decode algorithm to a decoder input derived from the detected output to yield the data output. ### Claim 15 (depends on 14) The method of claim 14, wherein the attribute of the second data set is a number of global iterations through both the data detector circuit and the data decoder circuit applied to the second data set during the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is a number of global iterations through both the data detector circuit and the data decoder circuit applied to the first data set during the first defined amount of processing by the data processing circuit. ### Claim 16 (depends on 14) The method of claim 14, wherein the attribute of the second data set is a combination of a number of global iterations through both the data detector circuit and the data decoder circuit applied to the second data set during the second defined amount of processing by the data processing circuit and a number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and the corresponding attribute of the first data set is combination of a number of global iterations through both the data detector circuit and the data decoder circuit applied to the first data set during the first defined amount of processing by the data processing circuit and a number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit. ### Claim 17 (depends on 14) The method of claim 14, wherein the detector circuit is selected from a group consisting of: a Viterbi algorithm data detector circuit, and a maximum a posteriori data detector circuit. ### Claim 18 (depends on 14) The method of claim 14, wherein the decoder circuit is a low density parity check decoder circuit. ### Claim 19 A storage device, the storage device comprising: a storage medium; a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to information on the storage medium; a read channel circuit including: an analog to digital converter circuit operable to sample an analog signal derived from the sensed signal to yield a series of digital samples; an equalizer circuit operable to equalize the digital samples to yield a first data set and a second data set; a data processing circuit operable to apply a data processing algorithm to a processing input to yield a data output; an input buffer operable to maintain at least a first data set and a second data set, wherein the first data set completed a first defined amount of processing by the data processing circuit without converging, and wherein the second data set is yet to complete a second defined amount of processing by the data processing circuit; a kick out circuit operable to compare an attribute of the second data set to a corresponding attribute of the first data set to determine whether the second data set will be maintained in the input buffer for additional processing after the second defined amount of processing by the data processing circuit; and wherein each of the first data set and the second data set are selectable as the processing input. ### Claim 20 (depends on 19) The storage device of claim 19, wherein the (a) attribute of the second data set and the (b) corresponding attribute of the first data set are selected from a group consisting of: (1) (a) a number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and (b) a number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit; (2) (a) a number of iterations through the data processing circuit applied to the second data set during the second defined amount of processing by the data processing circuit, and (b) a number of iterations through the data processing circuit applied to the first data set during the first defined amount of processing by the data processing circuit; and (3) (a) a combination of the number of iterations through the data processing circuit applied to the second data set during the second defined amount of processing by the data processing circuit and the number of unsatisfied checks remaining at the end of the second defined amount of processing by the data processing circuit, and (b) a combination of the number of iterations through the data processing circuit applied to the first data set during the first defined amount of processing by the data processing circuit and the number of unsatisfied checks remaining at the end of the first defined amount of processing by the data processing circuit.