# US 2014/0157073 A1 · Self evaluation of system on a chip with multiple cores

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0157073 A1
- Document ID: US20140157073A1
- Status: Published application
- Kind: A1
- Application number: 13/707,365
- Filed: 2012-12-06
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven M. Douskey; Ryan A. Fitch; Michael J. Hamilton; Amanda R. Kaufer
- Web page: https://patentgrep.com/patent/US20140157073A1

## CPC

- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/31718: {Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis (mechanical aspects G01R31/2808, G01R31/2851)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

## Claims

### Claim 1

A method for testing cores on an integrated circuit comprising:
each core of a plurality of cores performing the steps of:
producing a local signature that characterizes a local core, wherein each core of the plurality of cores is considered the local core;
comparing the local signature to neighbor core signatures of a plurality of neighbor cores; and
producing a goodness value for the local core based on comparing the local signature to the plurality of neighbor core signatures.

### Claim 2 (depends on 1)

The method of claim 1 further comprising the step of:
determining a partial good status of the integrated circuit from the goodness values from the plurality of cores.

### Claim 3 (depends on 1)

The method of claim 1 further comprising the step of:
outputting a characterization map for all cores with goodness values from each of the plurality of cores.

### Claim 4 (depends on 1)

The method of claim 1 wherein the compare of the local signature to the neighbor core signatures of the plurality of neighbor cores is a parallel compare.

### Claim 5 (depends on 1)

The method of claim 1 wherein the compare of the local signature to the neighbor core signatures of the plurality of neighbor cores is a serial compare.

### Claim 6 (depends on 1)

The method of claim 1 wherein the compare is a core centric serial compare of the local signature by shifting a predefined number of neighbor core signatures and comparing the local core signature with the shifted neighbor core signatures to produce results for each compare.

### Claim 7 (depends on 6)

The method of claim 6 further comprising the step of evaluating the results for each compare against a threshold to determine the goodness value for the local core and to mark cores under the threshold as bad, and wherein the goodness value for each of the plurality of cores is used to produce a partial good status for the integrated circuit.

### Claim 8 (depends on 7)

The method of claim 7 wherein the goodness values for all the cores in the integrated circuit are collected into a characterization map.

### Claim 9 (depends on 6)

The method of claim 6 further comprising the step of performing the core centric serial compare in multiple passes and bypasses compares of local cores where a previous pass indicated mismatch compares exceeding a threshold.

### Claim 10 (depends on 1)

The method of claim 1 wherein the integrated circuit is a system on a chip (SoC) and the core is a microprocessor core.