# US 2014/0157072 A1 · Self evaluation of system on a chip with multiple cores

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- Number: US 2014/0157072 A1
- Document ID: US20140157072A1
- Status: Published application
- Kind: A1
- Application number: 13/705,353
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Steven M. Douskey; Ryan A. Fitch; Michael J. Hamilton; Amanda R. Kaufer
- Web page: https://patentgrep.com/patent/US20140157072A1

## CPC

- G01R 31/31703: {Comparison aspects, e.g. signature analysis, comparators (concerning scan tests G01R31/318566; concerning testers G01R31/3193)}
- G01R 31/31718: {Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis (mechanical aspects G01R31/2808, G01R31/2851)}
- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method and structure tests a system on a chip (SoC) or other integrated circuit having multiple cores for chip characterization to produce a partial good status. A Self Evaluation Engine (SEE) on each core creates a quality metric or partial good value for the core. The SEE executes one or more tests to create a characterization signature for the core. The SEE then compares the characterization signature of a core with a characterization signature of neighboring cores to determine the partial good value for the core. The SEE may output a result to create a full characterization map for detailed diagnostics or a partial good map with values for all cores to produce a partial good status for the entire SoC.

## Claims

### Claim 1

An integrated circuit comprising:
a plurality of cores wherein each of the plurality of cores is considered a local core with a plurality of neighboring cores, wherein each local core further comprises:
a self test mechanism that executes at least one test on the local core and produces a local signature for the local core where the local signature characterizes the local core; and
a self evaluation engine (SEE) that compares the local signature with a plurality of neighbor core signatures produced by the plurality of neighboring cores to determine a goodness value for the local core.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 wherein the SEE performs a parallel compare of the local signature with the plurality of neighbor core signatures produced by the plurality of neighboring cores.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 wherein the SEE performs a serial compare of the local signature with the plurality of neighbor core signatures produced by the plurality of neighboring cores.

### Claim 4 (depends on 3)

The integrated circuit of claim 3 wherein the SEE performs a full serial compare of the local signature with the plurality of neighbor core signatures produced by the plurality of neighboring cores.

### Claim 5 (depends on 4)

The integrated circuit of claim 4 wherein the SEE performs a core centric serial compare of the local signature by shifting a predefined number of neighbor core signatures produced from the plurality of neighboring cores and comparing the local core signature with the neighbor core signature to produce results for each compare.

### Claim 6 (depends on 5)

The integrated circuit of claim 5 wherein the SEE evaluates the results for each compare against a threshold to determine a goodness value for the local core which is used to produce a partial good status for the integrated circuit.

### Claim 7 (depends on 6)

The integrated circuit of claim 6 wherein the goodness values for all the cores in the integrated circuit are collected into a characterization map.

### Claim 8 (depends on 5)

The integrated circuit of claim 5 wherein the SEE further performs the core centric serial compare in multiple passes and bypasses compares of local cores where a previous pass indicated mismatch compares exceeding a threshold.

### Claim 9 (depends on 1)

The integrated circuit of claim 1 wherein the integrated circuit is a system on a chip (SoC) and the core is a microprocessor core.

### Claim 10

An integrated circuit with a system on a chip (SoC) comprising:
a plurality of microprocessor cores on the integrated circuit wherein each microprocessor core of the plurality of microprocessor cores is considered a local core with a plurality of neighboring cores, wherein each local core further comprises:
a self test mechanism that executes at least one test on the local core and produces a local signature for the local core where the local signature characterizes the local core; and
a self evaluation engine (SEE) that performs a core centric serial compare of the local signature by comparing the local signature with a predefined number of neighbor core signatures shifted from the plurality of neighboring cores to produce results for each compare, wherein the SEE evaluates the results for each compare against a threshold to determine a goodness value, wherein the goodness value for each of the plurality of cores is used to produce a partial good status for the integrated circuit.

### Claim 11 (depends on 10)

The integrated circuit of claim 10 wherein the SEE performs the core centric compare in multiple passes and bypasses compares of local cores where a previous pass indicated mismatch compares exceeding a threshold.

### Claim at position 12

12-21. (canceled)