# US 2014/0157070 A1 · Selectively accessing test access ports in a multiple test access port environment

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- Number: US 2014/0157070 A1
- Document ID: US20140157070A1
- Status: Published application
- Kind: A1
- Application number: 14/173,473
- Filed: 2014-02-05
- Published: 2014-06-05
- Earliest claimed: 1996-08-30
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US20140157070A1

## CPC

- G01R 31/3177: Testing of logic operation, e.g. by logic analysers
- G01R 31/318536: {Scan chain arrangements, e.g. connections, test bus, analog signals}
- G01R 31/318555: {Control logic}
- G01R 31/318558: {Addressing or selecting of subparts of the device under test}
- G01R 31/318563: {Multiple simultaneous testing of subparts}
- G01R 31/318572: {Input/Output interfaces}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20).

## Claims

### Claim 1

An integrated circuit comprising:
A. a test data in lead, a test data out lead, a test clock lead, and a test mode select lead;
B. first test access port circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the first test access port circuitry having a first enable input and having a first select output;
C. second test access port circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the second test access port circuitry having a second enable input and having a second select output; and
D. linking module circuitry having a test data input coupled to the test data in lead, a test data output coupled to the test data out lead, a test clock input coupled to the test clock lead, and a test mode select input coupled to the test mode select lead, the linking module circuitry having a first enable output connected to the first enable input and a second enable output connected to the second enable input, the linking module circuitry including:
i. a first gate having a first select input connected to the first select output, a first enable input connected to the first enable output, and a first output; and
ii. a second gate having a second select input connected to the second select output, a second enable input connected to the second enable output, and a second output.

### Claim 2 (depends on 1)

The integrated circuit of claim 1 in which the first and second gates are AND gates.

### Claim 3 (depends on 1)

The integrated circuit of claim 1 in which the linking module circuitry includes state machine circuitry having a clock input coupled to the test clock lead, a mode select input coupled to the test mode select lead, and a select input coupled to the outputs of the first and second gates.

### Claim 4 (depends on 1)

The integrated circuit of claim 1 including an OR gate having inputs connected to the outputs of the first and second gates and having a select output.

### Claim 5 (depends on 4)

The integrated circuit of claim 4 in which the linking module circuitry includes state machine circuitry having a clock input coupled to the test clock lead, a mode select input coupled to the test mode select lead, and a select input connected to the output of the OR gate.