# US 2014/0157069 A1 · Semiconductor inspection apparatus and semiconductor inspection method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157069 A1 - Document ID: US20140157069A1 - Status: Published application - Kind: A1 - Application number: 14/020,203 - Filed: 2013-09-06 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Masami Nishizono - Web page: https://patentgrep.com/patent/US20140157069A1 ## CPC - G06F 11/2273: {Test methods} - G01R 31/31908: {Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns} - G01R 31/2894: {Aspects of quality control [QC] (G01R31/31718 takes precedence; program control for QC G05B19/41875)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A semiconductor inspection apparatus has a test-program execution part, a signal-condition detection part, a test-time calculation part to calculate an optimum test time having a duration from a period of the unstable region to a certain period at a leading portion of the stable region subsequent to the unstable region based on the unstable and stable regions detected by the signal-condition detection part, a test-program modification part to reflect the optimum test time in the test program, and a signal waveform importing part to import a signal at the signal output pin of the device to be tested based on a test time written in the test program in which the optimum test time is reflected. The test-program execution part executes the test program again after the optimum test time is reflected in the test program by the test-program modification part. ## Claims ### Claim 1 A semiconductor inspection apparatus comprising: a test-program execution part configured to execute a test program by applying a specific signal to a test-signal input pin of a device to be tested in accordance with the test program; a signal-condition detection part configured to detect an unstable region and a stable region of a signal at a signal output pin of the device to be tested while the test program is executed; a test-time calculation part configured to calculate an optimum test time having a duration from a period of the unstable region to a certain period at a leading portion of the stable region subsequent to the unstable region based on the unstable and stable regions detected by the signal-condition detection part; a test-program modification part configured to reflect the optimum test time in the test program; and a signal waveform importing part configured to import a signal at the signal output pin of the device to be tested based on a test time written in the test program in which the optimum test time is reflected, wherein the test-program execution part executes the test program again after the optimum test time is reflected in the test program by the test-program modification part. ### Claim 2 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein the optimum test time has a duration minimum required for correctly importing a signal at the signal output pin. ### Claim 3 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein the test-program modification part replaces a test time written in the test program with the optimum test time. ### Claim 4 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein, just before an end of the test time written in the test program, the signal waveform importing part imports a signal at the corresponding signal output pin. ### Claim 5 (depends on 4) The semiconductor inspection apparatus of claim 4, wherein the signal waveform importing part imports the signal at the corresponding signal output pin after the signal has shifted from the unstable region to the stable region. ### Claim 6 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein, when there are a plurality of signal output pins, the test-time calculation part calculates an optimum test time for each signal output pin. ### Claim 7 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein the unstable region is a region in which a signal level of a signal at the corresponding signal output pin starts to vary and is still unstable, and the stable region is a region subsequent to the unstable region, in which the signal level is stable. ### Claim 8 (depends on 1) The semiconductor inspection apparatus of claim 1, wherein the signal-condition detection part detects the unstable and stable regions whenever the test-program execution part executes the test program. ### Claim 9 A semiconductor inspection method comprising: executing a test program by applying a specific signal to a test-signal input pin of a device to be tested in accordance with the test program; detecting an unstable region and a stable region of a signal at a signal output pin of the device to be tested while the test program is executed; calculating an optimum test time having a duration from a period of the unstable region to a certain period at a leading portion of the stable region subsequent to the unstable region based on the detected unstable and stable regions; reflecting the optimum test time in the test program; and importing a signal at the signal output pin of the device to be tested based on a test time written in the test program in which the optimum test time is reflected. ### Claim 10 (depends on 9) The method of claim 9, wherein the optimum test time has a duration minimum required for correctly importing a signal at the signal output pin. ### Claim 11 (depends on 9) The method of claim 9, wherein a test time written in the test program is replaced with the optimum test time. ### Claim 12 (depends on 9) The method of claim 9, wherein, just before an end of the test time written in the test program, the importing imports a signal at the corresponding signal output pin. ### Claim 13 (depends on 12) The method of claim 12, wherein the importing imports the signal at the corresponding signal output pin after the signal has shifted from the unstable region to the stable region. ### Claim 14 (depends on 9) The method of claim 9, wherein, when there are a plurality of signal output pins, the calculating calculates an optimum test time for each signal output pin. ### Claim 15 (depends on 9) The method of claim 9, wherein the unstable region is a region in which a signal level of a signal at the corresponding signal output pin starts to vary and is still unstable, and the stable region is a region subsequent to the unstable region, in which the signal level is stable. ### Claim 16 (depends on 9) The method of claim 9, wherein the detecting detects the unstable and stable regions whenever the test-program execution part executes the test program.