# US 2014/0157066 A1 · Methods and apparatuses for memory testing with data compression > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157066 A1 - Document ID: US20140157066A1 - Status: Published application - Kind: A1 - Application number: 13/693,899 - Filed: 2012-12-04 - Published: 2014-06-05 - Earliest claimed: 2012-12-04 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Jason M. Johnson; Justin Wood; Gregory S. Hendrix; Mark D. Franklin; Daniel F. Eichenberger - Web page: https://patentgrep.com/patent/US20140157066A1 ## CPC - G11C 29/40: using compression techniques - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Apparatuses and methods for memory testing with data compression is described. An example apparatus includes a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory. Each of the latch test circuits is configured to receive test data and is configured to latch data from the corresponding global data line or a corresponding mask bit. Each of the plurality of latch test circuits is further configured to output data based at least in part on the corresponding mask bit. A comparison circuit is coupled to an output of each of the latch test circuits and is configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicative of whether all the output data matches. ## Claims ### Claim 1 An apparatus, comprising: a plurality of latch test circuits, wherein each of the plurality of latch test circuits is coupled to a corresponding global data line of a memory, wherein each of the latch test circuits is configured to receive test data and configured to latch data from the corresponding global data line, and configured to latch a corresponding mask bit, each of the plurality of latch test circuits further configured to output data based on the corresponding mask bit; and a comparison circuit coupled to an output of each of the latch test circuits and configured to compare output data provided by each of the latch test circuits and provide a comparator output having a logical value indicating whether the output data matches. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the output data provided by each of the latch test circuits is one of the data received from the respective memory or the test data. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the output data provided by each of the latch test circuits is the data from the respective memory cell when the mask bit has a first logical value and wherein the output data provided by each of the latch test circuits is the test data when the corresponding mask bit has a second logical value. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein each of the latch test circuits includes a corresponding mask latch circuit configured to store the corresponding mask bit. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein each of the corresponding mask latch circuits is coupled to a mask latch read enable signal, and wherein the output data provided by each of the latch test circuits is further based on the mask latch read enable signal. ### Claim 6 (depends on 2) The apparatus of claim 2, wherein each of the latch test circuits includes a corresponding data latch circuit configured to store the data from the respective memory. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein each of the latch test circuits includes a corresponding selection circuit configured to select, based on the corresponding mask bit, one of data from a respective memory via the corresponding global data line or the test data. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein each of the corresponding selection circuits includes a multiplexer having a first input configured to receive the data from a respective memory via the corresponding global data line, a second input configured to receive the test data, and a control input configured to receive the corresponding mask bit data. ### Claim 9 An apparatus, comprising: a memory array coupled to the plurality of global data lines, the memory array including a plurality of memory cells; a data compression circuit coupled to the plurality of global data lines via a corresponding sense amplifier circuit, the data compression circuit comprising: a plurality of latch test circuits, wherein each of the plurality of latch test circuits is configured to receive memory data from a respective global data line, and configured to receive a mask bit and test data, each of the latch test circuits configured to provide the memory data as an output responsive to the mask bit having a first logical value and to provide the test data responsive to the mask bit having a second logical value; and a comparison circuit coupled to an output of each of the latch test circuits, the comparison circuit configured to compare output data provided by each of the plurality of latch test circuits for matching logical values. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein data stored at the plurality of memory cells of the memory array is a test pattern. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the corresponding mask bit is driven on the global data line during a write operation while the corresponding plurality of memory cells are disabled, and wherein the corresponding mask bit is read from the corresponding global data line during a read operation. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the comparison of the output data by the comparison circuit includes comparing output data received from each of the plurality of latch test circuits against one another. ### Claim 13 (depends on 9) The apparatus of claim 9, further comprising an error flag generator coupled to the comparison circuit, and configured to receive comparison results from the comparison circuit and to generate one or more error flags based on the comparison results. ### Claim 14 A method, comprising: latching mask data at a data compression circuit of a memory; after latching the mask data, latching memory data; receiving a test data signal; providing output data to a comparator circuit based on the mask data, wherein the output data includes the memory data or the test data signal. ### Claim 15 (depends on 14) The method of claim 14, further comprising receiving a load enable signal, wherein latching the mask data is conditioned upon the a load enable signal being activated. ### Claim 16 (depends on 15) The method of claim 15, wherein latching the mask data comprises: receiving the mask data from global data lines corresponding to the data queue of the memory; and latching the mask data at a mask latch circuit. ### Claim 17 (depends on 16) The method of claim 16, wherein latching the mask data further comprises: enabling sense amplifiers coupled to the global data lines; disabling word lines to corresponding to memory cells coupled to the global data lines; writing the mask data to the global data lines, wherein the mask data is stored at the sense amplifiers; and reading the mask data from the sense amplifiers via the global data lines. ### Claim 18 (depends on 14) The method of claim 14, wherein providing, based on the mask data, the memory data or the test data signal to a comparator circuit comprises: selecting a memory data bit of the memory data corresponding to a particular global data line of the global data lines when a mask bit of the mask data corresponding to the particular global data line has a first logical value; and selecting the test data signal when the mask bit corresponding to the particular global data line has a second logical value. ### Claim 19 (depends on 14) The method of claim 14, further comprising receiving a mask latch read enable signal, wherein providing the memory data or the test data signal to a comparator circuit is further based on the mask latch read enable signal. ### Claim 20 (depends on 14) The method of claim 14, wherein a value of the test data signal is one of a logical high value or a logical low value. ### Claim 21 (depends on 14) The method of claim 14, further comprising, writing the memory data to the memory prior to latching the mask data. ### Claim 22 (depends on 14) The method of claim 14, further comprising, after latching the mask data, prefetching the memory data, wherein the prefetched data is driven on global data lines coupled to the data queue. ### Claim 23 (depends on 14) The method of claim 14, further comprising comparing bits included in the output data against one another to generate an internal error flag.