# US 2014/0157065 A1 · Method and system for providing a smart memory architecture

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- Number: US 2014/0157065 A1
- Document ID: US20140157065A1
- Status: Published application
- Kind: A1
- Application number: 13/936,134
- Filed: 2013-07-05
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Adrian E. ONG
- Web page: https://patentgrep.com/patent/US20140157065A1

## CPC

- G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details}
- G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00)
- G06F 15/7821: {Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory}
- G06F 21/00: Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 11/16: using elements in which the storage effect is based on magnetic spin effect
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The system may include a smart memory controller capable of performing a bit error rate built-in self test. The smart memory control may include bit error rate controller logic configured to control the bit error rate built-in self test. A write error rate test pattern generator may generate a write error test pattern for the bit error rate built-in self test. A read error rate test pattern generator may generate a read error test pattern for the built-in self test. The smart memory controller may internally generate an error rate timing pattern, perform built-in self test, measure the resulting error rate, automatically adjust one or more test parameters based on the measured error rate, and repeat the built-in self test using the adjusted parameters.

## Claims

### Claim 1

A method for providing a bit error rate built-in self test on a memory device, the method comprising:
entering a test mode;
internally generating, by the memory device, an error rate timing pattern;
performing, by the memory device, the bit error rate built-in self test based on the internally generated error rate timing pattern;
measuring an error rate resulting from the bit error rate built-in self test; and
repeating the bit error rate built-in self test.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
adjusting, based on the measured error rate, one or more test parameters,
wherein repeating includes repeating the bit error rate built-in self test using the adjusted parameters.

### Claim 3 (depends on 2)

The method of claim 2, wherein:
performing the bit error rate built-in self test includes performing a write error rate test;
measuring includes measuring a write error rate;
adjusting includes adjusting, based on the measured write error rate, the one or more test parameters; and
repeating includes repeating the write error rate test using the adjusted parameters.

### Claim 4 (depends on 2)

The method of claim 2, wherein:
performing the bit error rate built-in self test includes performing a read error rate test;
measuring includes measuring a read error rate;
adjusting includes adjusting, based on the measured read error rate, the one or more test parameters; and
repeating includes repeating the read error rate test using the adjusted parameters.

### Claim 5 (depends on 1)

The method of claim 1, wherein entering the test mode further comprises:
receiving one or more mode register set commands; and
entering the test mode responsive to the one or more mode register set commands.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
receiving one or more mode register set commands; and
configuring the one or more test parameters responsive to the one or more mode register set commands.

### Claim 7 (depends on 6)

The method of claim 6, wherein configuring the one or more test parameters further comprises:
setting at least one of a start voltage, a voltage range, and a voltage step.

### Claim 8 (depends on 6)

The method of claim 6, wherein configuring the one or more test parameters further comprises:
setting at least one of a read pulse width and a write pulse width.

### Claim 9 (depends on 1)

The method of claim 1, wherein adjusting the one or more test parameters further comprises:
automatically setting a read voltage to a next programmed voltage level.

### Claim 10 (depends on 1)

The method of claim 1, wherein adjusting the one or more test parameters further comprises:
automatically setting a write voltage to a next programmed voltage level.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
automatically re-assigning memory space within the memory device when the measured error rate exceeds a predefined threshold.

### Claim 12

A method for providing a bit error rate built-in self test on a memory device, the method comprising:
performing, by the memory device, at least one of a write error rate built-in self test and a read error rate built-in self test;
analyzing results of the at least one of the write error rate built-in self test and the read error rate built-in self test; and
automatically adjusting one or more test parameters responsive to the analysis.

### Claim 13 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a voltage level for an address location.

### Claim 14 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a voltage level for an address segment.

### Claim 15 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a voltage level for an entire chip associated with the memory device.

### Claim 16 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a pulse width for an address location.

### Claim 17 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a pulse width for an address segment.

### Claim 18 (depends on 12)

The method of claim 12, wherein automatically adjusting further comprises:
automatically adjusting a pulse width for an entire chip associated with the memory device.

### Claim 19

A memory device, comprising:
bit error rate control logic configured to control a bit error rate built-in self test;
an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;
a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and
a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.

### Claim 20 (depends on 19)

The memory device of claim 19, further comprising:
logic configured to count cycles of the bit error rate built-in self test.

### Claim 21 (depends on 19)

The memory device of claim 19, further comprising:
a write error rate cycle count register configured to store a number of write cycles; and
a read error rate cycle count register configured to store a number of read cycles.

### Claim 22 (depends on 19)

The memory device of claim 19, further comprising:
a pulse width generator circuit; and
a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

### Claim 23 (depends on 19)

The memory device of claim 19, further comprising:
a voltage generator; and
a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

### Claim 24 (depends on 23)

The memory device of claim 23, further comprising:
a write error counter configured to count a number of write errors of the bit error rate built-in self test; and
a read error counter configured to count a number of read errors of the bit error rate built-in self test.

### Claim 25

A system for providing a bit error rate built-in self test, comprising:
a bus;
a memory coupled to the bus; and
a smart memory controller, including:
bit error rate control logic configured to control a bit error rate built-in self test;
an on-chip oscillator configured to generate an internal reference clock for the bit error rate built-in self test;
a write error rate test pattern generator configured to generate a write error test pattern for the bit error rate built-in self test; and
a read error rate test pattern generator configured to generate a read error test pattern for the bit error rate built-in self test.

### Claim 26 (depends on 25)

The system of claim 25, wherein the smart memory controller further comprises:
logic configured to count cycles of the bit error rate built-in self test.

### Claim 27 (depends on 25)

The system of claim 25, wherein the smart memory controller further comprises:
a write error rate cycle count register configured to store a number of write cycles; and
a read error rate cycle count register configured to store a number of read cycles.

### Claim 28 (depends on 25)

The system of claim 25, wherein the smart memory controller further comprises:
a pulse width generator circuit; and
a pulse width register configured to provide code to select an intended pulse width delay in the pulse width generator circuit.

### Claim 29 (depends on 25)

The system of claim 25, wherein the smart memory controller further comprises:
a voltage generator; and
a voltage regulator register configured to produce a code to select a voltage bias level in the voltage generator.

### Claim 30 (depends on 29)

The system of claim 29, wherein the smart memory controller further comprises:
a write error counter configured to count a number of write errors of the bit error rate built-in self test; and
a read error counter configured to count a number of read errors of the bit error rate built-in self test.