# US 2014/0157059 A1 · Data processing device, microcontroller, and self-diagnosis method of data processing device

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- Number: US 2014/0157059 A1
- Document ID: US20140157059A1
- Status: Published application
- Kind: A1
- Application number: 14/174,468
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2012-05-31
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Akira HOSOTANI
- Web page: https://patentgrep.com/patent/US20140157059A1

## CPC

- G06F 11/2273: {Test methods}
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 29/38: Response verification devices
- G11C 2029/0409: {Online test}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A data processing device according to the present invention includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

## Claims

### Claim 1

A test method for a data processing device including a read-modify-write function, the test method comprising the steps of:
(a) performing the read-modify-write function for first data by the data processing device to generate second data; and
(b) comparing the second data with expected data by the data processing unit,
wherein the data processing device invalidates other data processing during a period between the steps (a) and (b).

### Claim 2 (depends on 1)

The test method according to claim 1, wherein the data processing device further includes a memory,
wherein the data processing device invalidates a memory access processing during the period between the steps (a) and (b).

### Claim 3 (depends on 1)

The test method according to claim 1, wherein the data processing device further includes a first storage unit that stores the first data.

### Claim 4 (depends on 1)

The test method according to claim 1, wherein the data processing device further includes a second storage unit that stores the second data.

### Claim 5 (depends on 1)

The test method according to claim 1, wherein the second data is generated by replacing a part of the first data with modification data.

### Claim 6 (depends on 1)

The test method according to claim 1, further comprising:
(c) setting a timing for the steps (a) and (b) by the data processing unit,
wherein the steps (a) and (b) are executed by the data processing unit at the timing.

### Claim 7

A test method for a data processing device including a read-modify-write function, the test method comprising the steps of:
(a) writing self-diagnosis data by the data processing device;
(b) performing self-diagnosis of the read-modify-function using the self-diagnosis data by the data processing device; and
(c) reading self-diagnosis output data by the data processing device,
wherein the data processing device invalidates other data processing at one of the steps (a), (b) and (c).

### Claim 8 (depends on 7)

The test method according to claim 7, wherein the data processing device further includes a memory,
wherein the data processing device invalidates a memory access processing at one of the steps (a), (b) and (c).

### Claim 9 (depends on 7)

The test method according to claim 7, further comprising:
(d) comparing the self-diagnosis output data with expected data by the data processing device.

### Claim 10 (depends on 7)

The test method according to claim 7, wherein the self-diagnosis output data is generated by replacing a part of the self-diagnosis data with modification data.

### Claim 11 (depends on 7)

The test method according to claim 7, wherein the data processing device further includes a memory,
wherein the data processing device invalidates a memory access processing at one of the steps (a), (b) and (c).

### Claim 12 (depends on 7)

The test method according to claim 7, further comprising:
(d) setting a timing for the steps (b) and (c) by the data processing unit,
wherein the steps (b) and (c) are executed by the data processing device at the timing.

### Claim 13

A microcontroller comprising:
a first data processing unit;
a second data processing unit;
a memory; and
a read-modify-write unit,
wherein when the first data processing unit executes a self-diagnosis of the read-modify-write unit, an access from the second data processing unit to the memory is invalidated.

### Claim 14 (depends on 13)

The microcontroller according to claim 13, wherein the first data processing unit is a first Central Processing Unit (CPU) and the second data processing unit is a second CPU or a Direct Memory Access Controller (DMAC).

### Claim 15 (depends on 13)

The microcontroller according to claim 13, further comprising:
an Error Correcting Code (ECC) unit,
wherein the read-modify-write unit is configured to execute a read-modify-write function with the ECC unit.

### Claim 16 (depends on 13)

The microcontroller according to claim 13, further comprising:
a first storage unit that stores first data,
wherein the read-modify-write unit is configured to generate second data by replacing a part of the first data with modification data when the self-diagnosis is executed.

### Claim 17 (depends on 16)

The microcontroller according to claim 16, further comprising:
a second storage unit that sores the second data.