# US 2014/0157055 A1 · Memory subsystem command bus stress testing

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- Number: US 2014/0157055 A1
- Document ID: US20140157055A1
- Status: Published application
- Kind: A1
- Application number: 13/706,196
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Intel Corporation
- Inventors: CHRISTOPHER P. MOZAK; Thoedore Z. Schoenborn; James M. Shehadi; David G. Ellis; Tomer Levy; Zvika Greenfield
- Web page: https://patentgrep.com/patent/US20140157055A1

## CPC

- G06F 11/263: Generation of test inputs, e.g. test vectors, patterns or sequences {; with adaptation of the tested hardware for testability with external testers}
- G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C 29/025: {in signal lines}
- G11C 29/06: Acceleration testing
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory subsystem includes logic buffer coupled to a command bus between a memory controller and a memory device. The logic buffer detects that the memory controller places the command bus in a state where the memory controller does not drive the command bus with a valid executable memory device command. In response to detecting the state of the command bus, the logic buffer generates a signal pattern and injects the signal pattern on the command bus after a scheduler of the memory controller to drive the command bus with the signal pattern.

## Claims

### Claim 1

A memory subsystem comprising:
a memory device to store data and execute memory device commands to access and manage the data;
a memory controller coupled to the memory device via a data bus and via a command bus, the memory controller to drive the command bus with memory device commands; and
a buffer coupled to the command bus, the buffer including logic to detect that the at least a portion of the command bus is in a state where the memory controller does not drive the portion with a valid executable memory device command, generate a signal pattern in response to detecting the state, the signal pattern generated based on the detected state, and inject the signal pattern on the command bus after a scheduler of the memory controller to drive the portion of the command bus with the signal pattern.

### Claim 2 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to detect a deselect cycle.

### Claim 3 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to detect a no operation (NOP) command.

### Claim 4 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to detect a select cycle where at least a portion of the command bus is driven with a valid executable memory device command.

### Claim 5 (depends on 4)

The memory subsystem of claim 4, wherein the buffer logic is to override at least a portion of the command bus driven with a valid executable memory device command to drive the portion with the signal pattern.

### Claim 6 (depends on 1)

The memory subsystem of claim 1, wherein the portion comprises one or more fields of a command signal not used for a particular command on the command bus.

### Claim 7 (depends on 1)

The memory subsystem of claim 1, wherein the portion of the command signal comprises a specific command field.

### Claim 8 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to further check a synchronization signal to control when to generate the signal pattern.

### Claim 9 (depends on 8)

The memory subsystem of claim 8, wherein the buffer logic is to further monitor the command bus for valid executable commands and synchronize to the valid executable commands, and when the portion of the command bus does not include a valid executable command, the buffer logic is to inject the signal pattern onto the portion of the bus to keep the bus full.

### Claim 10 (depends on 8)

The memory subsystem of claim 8, wherein the buffer logic is to save and restore a signal pattern selection state based on the synchronization signal.

### Claim 11 (depends on 8)

The memory subsystem of claim 8, wherein the synchronization signal comprises a signal from the scheduler.

### Claim 12 (depends on 8)

The memory subsystem of claim 8, wherein the synchronization signal comprises a signal from the memory controller or a signal from a test engine coupled to the memory controller.

### Claim 13 (depends on 8)

The memory subsystem of claim 8, wherein the synchronization signal comprises one or more specific memory device commands.

### Claim 14 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to generate the signal pattern by selecting bits of an M×N buffer array of bits to drive the portion of the command bus.

### Claim 15 (depends on 14)

The memory subsystem of claim 14, wherein N is a number of bits equal to a width of the command bus.

### Claim 16 (depends on 14)

The memory subsystem of claim 14, wherein the buffer logic is to apply Y-bit selection logic that generates a Boolean combination of bits of the buffer array, where 2̂Y is a number equal to or greater than M, to select from M rows of N bits.

### Claim 17 (depends on 16)

The memory subsystem of claim 16, wherein each bit of the Y-bit selection logic is associated with a different pattern type.

### Claim 18 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic is to generate different signal patterns based on whether the detected state is a select cycle where at least a portion of the command signal is driven with a valid executable memory device command, or a deselect cycle where no portion of the command signal is driven with a valid executable memory device command.

### Claim 19 (depends on 18)

The memory subsystem of claim 18, wherein the buffer logic further includes select cycle pattern generation logic and separate deselect cycle pattern generation logic, and is to generate the different signal patterns with the separate pattern generation logic based on whether the buffer logic detects a select cycle or a deselect cycle.

### Claim 20 (depends on 1)

The memory subsystem of claim 1, wherein the memory controller drives the command bus at a same rate as a data bus between the memory controller and the memory device, and wherein generating the signal pattern further comprises running pattern selection hardware at a double rate to perform multiple operations of pattern generation per clock cycle.

### Claim 21 (depends on 20)

The memory subsystem of claim 20, wherein the buffer logic is to provide even and odd signal patterns to specific lanes of the command bus corresponding to how the lanes are combined in a parallel-in, serial-out logic device.

### Claim 22 (depends on 1)

The memory subsystem of claim 1, wherein the buffer logic further includes different pattern generators to generate signal patterns of different types, the different types of signal patterns selected from a linear shift feedback register (LSFR), a square wave generator, or a pattern buffer.

### Claim 23

An electronic device comprising:
a memory subsystem including
a memory device to store data and execute memory device commands to access and manage the data;
a memory controller coupled to the memory device via a data bus and via a command bus, the memory controller to drive the command bus with memory device commands; and
a buffer coupled to the command bus, the buffer including logic to detect that the at least a portion of the command bus is in a state where the memory controller does not drive the portion with a valid executable memory device command, generate a signal pattern in response to detecting the state, the signal pattern generated based on the detected state, and inject the signal pattern on the command bus after a scheduler of the memory controller to drive the portion of the command bus with the signal pattern; and
a touchscreen display coupled to generate a display based on data stored in the memory subsystem.

### Claim 24 (depends on 23)

The electronic device of claim 23, wherein the buffer logic is to detect one of a select cycle where at least a portion of the command bus is driven with a valid executable memory device command, a deselect cycle, or a no operation (NOP) command.

### Claim 25 (depends on 23)

The electronic device of claim 23, wherein the buffer logic is to further check a synchronization signal to control when to generate the signal pattern.

### Claim 26 (depends on 23)

The electronic device of claim 23, wherein the buffer logic is to generate the signal pattern by selecting bits of an M×N buffer array of bits to drive the portion of the command bus.

### Claim 27

A method comprising:
detecting that at least a portion of command signal on a command bus between a memory controller and a memory device is in a state where the memory controller does not drive the portion with a valid executable memory device command;
generating a signal pattern in response to detecting the state, the signal pattern generated based on the detected state; and
injecting the signal pattern on the command bus after a scheduler of the memory controller to drive the portion of the command bus with the signal pattern.

### Claim 28 (depends on 27)

The method of claim 27, wherein detecting the state comprises detecting one of a select cycle where at least a portion of the command bus is driven with a valid executable memory device command, a deselect cycle, or a no operation (NOP) command.

### Claim 29 (depends on 27)

The method of claim 27, wherein detecting the state further comprises:
checking a synchronization signal received from the scheduler to control when the generating the signal pattern occurs.

### Claim 30 (depends on 27)

The method of claim 27, wherein generating the signal pattern comprises:
generating the signal pattern by selecting bits of an M×N buffer array of bits to drive the portion of the command bus.