# US 2014/0157054 A1 · Memory error identification based on corrupted symbol patterns > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157054 A1 - Document ID: US20140157054A1 - Status: Published application - Kind: A1 - Application number: 13/689,814 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Hewlett-Packard Development Company, L.P. - Applicants: Hewlett-Packard Development Cpmpany, L.P. - Inventors: Doe Hyun Yoon; Jichuan Chang; Naveen Muralimanohar - Web page: https://patentgrep.com/patent/US20140157054A1 ## CPC - G06F 11/006: {Identification (G06F11/2289 takes precedence)} - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/0751: {Error or fault detection not based on redundancy (power supply failures G06F1/30; network fault management H04L41/06)} - G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system includes a memory controller, a buffer, a first channel to couple the memory controller to the buffer, and a second channel to couple the buffer to a memory. The first channel and second channel are to transmit a codeword including a plurality of symbols. A symbol is formed from a plurality of bursts based on data access of the memory. The memory controller is to identify a memory error based on a corrupted symbol pattern of the codeword. The memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. ## Claims ### Claim 1 A system comprising: a memory controller; a buffer; a first channel having a first channel width, to couple the memory controller to the buffer; and a second channel having a second channel width, to couple the buffer to a memory; wherein a first channel width differs from a second channel width, and the first channel and second channel are to transmit a codeword including a plurality of symbols, wherein a symbol is formed from a plurality of bursts based on data access of the memory; and wherein the memory controller is to identify a type of memory error based on a corrupted symbol pattern of the codeword, wherein the memory controller is to discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being the type of memory error, according to the corrupted symbol pattern. ### Claim 2 (depends on 1) The system of claim 1, wherein the memory controller is to identify the type of memory error as the chip failure, based on identifying the corrupted symbol pattern including adjacent corrupted symbols per codeword. ### Claim 3 (depends on 1) The system of claim 1, wherein the memory controller is to identify the type of memory error as the pin failure of the first channel, based on identifying the corrupted symbol pattern including non-adjacent corrupted symbols per codeword. ### Claim 4 (depends on 3) The system of claim 3, wherein a spacing of the non-adjacent corrupted symbols corresponds to a function of a ratio of the first channel width and the second channel width. ### Claim 5 (depends on 1) The system of claim 1, wherein the memory controller is to identify the type of memory error as the pin failure of the second channel, based on identifying the corrupted symbol pattern including a corrupted symbol per codeword that is not adjacent to another corrupted symbol. ### Claim 6 (depends on 1) The system of claim 1, wherein the memory controller is to correct a plurality of corrupted symbols of the codeword, based on at least one check symbol included in the codeword. ### Claim 7 (depends on 1) The system of claim 1, wherein the plurality of symbols of the codeword include a check symbol for every eight data symbols. ### Claim 8 (depends on 1) The system of claim 1, wherein the memory is based on Double data rate (DDRx) synchronous dynamic random-access memory (SDRAM), where x is an integer corresponding to burst data transfer rate. ### Claim 9 (depends on 1) The system of claim 1, wherein each of the plurality of symbols is an 8-bit symbol based on a 2-burst, 4-bit transfer. ### Claim 10 A method, comprising: receiving a codeword across a first channel coupling a memory controller to a buffer, and a second channel coupling the buffer to a memory, wherein a first channel width differs from a second channel width, and the codeword includes a plurality of data symbols and at least one check symbol, wherein each of the plurality of symbols is formed from a plurality of bursts based on data access of the memory; correcting, using a memory controller and the at least one check symbol, a memory error based on a corrupted symbol pattern of the codeword; and discriminating between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. ### Claim 11 (depends on 10) The method of claim 10, further comprising applying an error-correcting code (ECC) to the codeword, based on the use of the check symbols. ### Claim 12 (depends on 11) The method of claim 11, wherein the ECC is Reed-Solomon coding. ### Claim 13 (depends on 12) The method of claim 12, further comprising storing an indication of a corrected first error, and correcting a second error based on the stored indication and erasure coding. ### Claim 14 A non-transitory computer readable medium having instructions stored thereon executable by a processor to cause a memory controller to: receive a codeword across a first channel, coupling a memory controller to a buffer, and a second channel coupling the buffer to a memory, wherein a first channel width differs from a second channel width, and the codeword includes a plurality of data symbols and at least one check symbol, wherein each of the plurality of symbols is formed from a plurality of bursts based on data access of the memory; correct, using the memory controller and the at least one check symbol, a memory error based on a corrupted symbol pattern of the codeword; and discriminate between a chip failure, a first pin failure of the first channel, and a second pin failure of the second channel, as being a type of the memory error, according to the corrupted symbol pattern. ### Claim 15 (depends on 14) The computer readable medium of claim 14, wherein the memory controller is to provide an indication of the type of error for diagnostic purposes.