# US 2014/0157045 A1 · Memory controller, memory system including the memory controller, and operating method performed by the memory controller

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- Number: US 2014/0157045 A1
- Document ID: US20140157045A1
- Status: Published application
- Kind: A1
- Application number: 14/096,824
- Filed: 2013-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Samsung Electronics Co., Ltd.
- Inventors: Hyun-joong Kim; Tae-young Oh
- Web page: https://patentgrep.com/patent/US20140157045A1

## CPC

- G11C 29/76: {using address translation or modifications}
- G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Provided are a memory controller, a memory system including the memory controller, and an operating method performed by the memory controller. The operating method includes operations of queuing a first command in a first queue, detecting a fail of a first address that corresponds to the first command, when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address, and outputting the second command and the second address from the first queue.

## Claims

### Claim 1

An operating method performed by a memory controller, the operating method comprising:
queuing a first command in a first queue;
detecting a fail of a first address that corresponds to the first command;
when the first address is determined as a fail address, queuing a second address and a second command in the first queue, wherein the second address is obtained by remapping the first address and the second command corresponds to the second address; and
outputting the second command and the second address from the first queue.

### Claim 2 (depends on 1)

The operating method of claim 1, wherein, when the first command exists in the first queue, the queuing of the second command comprises replacing the first command and the first address with the second address and the second command.

### Claim 3 (depends on 1)

The operating method of claim 1, further comprising, when the first command is a read command, blocking an output of first data to an external source and outputting second data to the external source, wherein the first data is received in response to the first command and the second data is received in response to the second command.

### Claim 4 (depends on 3)

The operating method of claim 3, further comprising determining whether the first address is a fail address by comparing the first data with the second data.

### Claim 5 (depends on 1)

The operating method of claim 1, wherein, when the first command is a write command, the second command and the second address are output, regardless of whether the first command and the first address are output.

### Claim 6 (depends on 1)

The operating method of claim 1, further comprising generating the first command and the first address by decoding a packet that is received from an external source.

### Claim 7 (depends on 1)

The operating method of claim 1, wherein the memory controller comprises a storing unit that stores address information of a defective cell of a semiconductor memory device, and
the detecting of the fail comprises comparing a match between the first address and the address information that is stored in the storing unit.

### Claim 8 (depends on 1)

The operating method of claim 1, wherein the second address is generated so that an access time corresponding to the second command is less than an access time corresponding to the first command.

### Claim 9 (depends on 1)

The operating method of claim 1, wherein the second command is controlled to be output from the first queue prior to other commands that are placed in the first queue before the second command.

### Claim 10 (depends on 1)

The operating method of claim 1, wherein, when the first address is detected as a normal address, the first command and the first address are output according to a queuing order of the first queue.

### Claim 11 (depends on 1)

The operating method of claim 1, wherein the first command is generated by decoding an external packet, and the second command requests a memory operation equal to a memory operation of the first command.

### Claim 12 (depends on 11)

The operating method of claim 11, wherein the memory controller comprises a content addressable memory (CAM) to perform the detecting,
the CAM receives and temporarily stores the first command, and
the temporarily stored first command is provided as the second command to the first queue.

### Claim 13 (depends on 1)

The operating method of claim 1, wherein the detecting of the fail occurs at a same time as the queuing of the first command or outputting the first command and the first address.

### Claim 14 (depends on 1)

The operating method of claim 1, wherein the first address corresponds to an address in a normal memory area of a semiconductor memory device and the second address corresponds to an address in a redundancy memory area of the semiconductor memory device.

### Claim 15

A memory controller comprising:
a decoder for decoding a packet and generating a command and an address that corresponds to the command;
a first queue for storing the command and the address;
a content addressable memory (CAM) for detecting a fail of a first address that corresponds to a first command, and when the first address is detected as a fail address, for outputting a second address and a second command to the first queue, wherein the second address is obtained by remapping the first address, and the second command corresponds to the second address; and
a controller input/output (controller I/O) for outputting the command and the address stored in the first queue.

### Claim 16 (depends on 15)

The memory controller of claim 15, wherein the decoder is connected to each of the first queue and the CAM, and the command and the address are provided in parallel to the first queue and the CAM.

### Claim 17 (depends on 15)

The memory controller of claim 15, wherein the CAM comprises:
a fail address storing unit for storing address information of a defective cell of a semiconductor memory device; and
a fail address detector for the detecting the fail of the first address by comparing a match between the first address and the address information of the defective cell.

### Claim 18 (depends on 15)

The memory controller of claim 15, wherein the fail address storing unit further stores remapping address information that corresponds to the address information of the defective cell, and
the fail address detector outputs the remapping address information as the second address, wherein the remapping address information corresponds to the first address.

### Claim 19 (depends on 15)

The memory controller of claim 15, wherein, when the first command exists in the first queue, the first address existing in the first queue is replaced with the second address.

### Claim 20 (depends on 15)

The memory controller of claim 15, further comprising an arbiter that is disposed between the first queue and the controller I/O and that controls an execution of a command stored in the first queue.

### Claim 21 (depends on 20)

The memory controller of claim 20, wherein, when the first command is a read command, the arbiter outputs an error data signal indicating that the first address corresponds to a fail address, and
the memory controller further comprises data blocking logic for blocking an output of first data that is received in response to the first command and for controlling second data, which is received in response to the second command, to be output to an external source, according to the error data signal.

### Claim 22

A memory system comprising:
a semiconductor memory device for storing data; and
a memory controller for queuing a first command in a queue, for simultaneously performing an operation of outputting the first command from the queue and an operation of detecting a fail of a first address that corresponds to the first command, and when the first address is detected as a fail address, for outputting a second address, which is obtained by remapping the first address, and a second command that corresponds to the second address.

### Claim 23 (depends on 22)

The memory system of claim 22, wherein the semiconductor memory device comprises a random access memory (RAM).

### Claim 24 (depends on 22)

The memory system of claim 22, wherein the semiconductor memory device comprises a cell array comprising a memory area and a redundancy area, and the second address indicates a cell which is positioned in the redundancy area.

### Claim 25 (depends on 22)

The memory system of claim 22, further comprising a dynamic random access memory (DRAM) interface between the memory controller and the semiconductor memory device.

### Claim 26

A memory controller comprising:
a decoder configured to decode a packet and generate a command and an address that corresponds to the command;
a content addressable memory (CAM) configured to:
store address information of a defective cell of a semiconductor memory device,
detect a fail of the address by comparing the address with the address information of the defective cell, and
according to a result of the detecting, output a remapping address; and
a queue configured to queue the command and the address that corresponds to the command, regardless of the result of the detecting, and additionally configured to queue the remapping address when the address corresponds to a fail address.

### Claim 27

A method for a memory device, the method comprising:
receiving a first command and a first address corresponding to the first command;
determining whether the first address corresponds to a fail address and concurrently storing the first command and first address in a queue;
when the first address corresponds to a fail address, storing a second address in the queue, the second address corresponding to the first address in the queue; and
when the first address does not correspond to a fail address, using the first address for the first command.

### Claim 28 (depends on 27)

The method of claim 27, further comprising:
when the first address is determined to correspond to the fail address before the first address is output from the queue, replacing the first address stored in the queue with the second address.

### Claim 29 (depends on 27)

The method of claim 27, further comprising:
if the first command is a write command:
when the first address is determined to correspond to the fail address after the first address is output from the queue, outputting the second address from the queue along with a command that corresponds to the first command;
when the first address is determined to correspond to the fail address before the first address is output from the queue, replacing the first address in the queue with the second address; and
if the first command is a read command:
when the first address is determined to correspond to the fail address after the first address is output from the queue, preventing a read operation for the first address; and
when the first address is determined to correspond to the fail address before the first address is output from the queue, replacing the first address in the queue with the second address.

### Claim 30 (depends on 27)

The method of claim 27, further comprising:
storing a set of fail addresses, including the first address, in a table;
subsequent to storing the second address in the queue or using the first address for the first command, determining whether the first address still corresponds to a fail address; and
if the first address no longer corresponds to a fail address, removing the fail address from the table.