# US 2014/0157035 A1 · Bit-Timing Symmetrization

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- Number: US 2014/0157035 A1
- Document ID: US20140157035A1
- Status: Published application
- Kind: A1
- Application number: 13/705,239
- Filed: 2012-12-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-05
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Achim Vowe
- Web page: https://patentgrep.com/patent/US20140157035A1

## CPC

- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 13/382: {using universal interface adapter}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A bus interface, for allowing a plurality of devices to communicate with one another via the bus, includes a bit timing symmetrization component for symmetrizing the bit stream. For an incoming bit stream, the bit timing symmetrization component further includes an input delay filter for delaying recessive to dominant edges for a given received bit stream and sampling the delayed input signal at the sample point. In one embodiment, bit timing synchronization may still be performed with the undelayed recessive to dominant edges. For an outgoing bit stream, the bit timing symmetrization component transmits a recessive bit, that followed a previously transmitted dominant bit, before the start of the next bit time, and transmits a dominant bit, that followed a previously transmitted recessive bit, with a delay of a configurable amount of time.

## Claims

### Claim 1

A bus interface for coupling a device to a bus, the bus allowing a plurality of devices to communicate with one another, the bus interface receiving and transmitting a bit stream from and to the bus, the bus interface comprising:
a bit timing symmetrization component configured to symmetrize the bit stream.

### Claim 2 (depends on 1)

The bus interface of claim 1, wherein the bit timing symmetrization component further comprises an input delay filter configured to delay an input signal received from the bit stream to improve the bit timing of the bit stream.

### Claim 3 (depends on 2)

The bus interface of claim 2, wherein the input delay filter is configured to delay a recessive to dominant edge for a given received bit stream.

### Claim 4 (depends on 2)

The bus interface of claim 2, further comprising a bit timing logic component, wherein the input delay filter is integrated within the bit timing logic component and wherein the received delayed input signal is delayed within the bit timing logic component.

### Claim 5 (depends on 2)

The bus interface of claim 2, wherein the input delay filter further comprises a dominant limit value and a recessive limit value which are configurable.

### Claim 6 (depends on 1)

The bus interface of claim 1, wherein the bit timing symmetrization component is configured to transmit a recessive bit that followed a previously transmitted dominant bit before a start of a next bit time.

### Claim 7 (depends on 1)

The bus interface of claim 1, wherein the bit timing symmetrization component is configured to delay a dominant bit that followed a previously transmitted recessive bit by a configurable amount of time.

### Claim 8 (depends on 1)

The bus interface of claim 1, wherein the bus system is a controlled area network (CAN) bus system.

### Claim 9

A bus system for receiving and transmitting a bit stream from and to a bus, the bus system comprising:
a bit timing symmetrization component configured to symmetrize the bit stream.

### Claim 10 (depends on 9)

The bus interface of claim 9, wherein the bit timing symmetrization component further comprises an input delay filter configured to delay an input signal received from the bit stream to improve the bit timing of the bit stream.

### Claim 11 (depends on 10)

The bus interface of claim 10, wherein the input delay filter is configured to delay recessive to dominant edge for a given received bit stream.

### Claim 12 (depends on 10)

The bus interface of claim 10, further comprising a bit timing logic component, wherein the input delay filter is integrated within the bit timing logic component and wherein the received delayed input signal is delayed within the bit timing logic component.

### Claim 13 (depends on 10)

The bus interface of claim 10, wherein the input delay filter further comprises a dominant limit value and a recessive limit value which are configurable.

### Claim 14 (depends on 9)

The bus interface of claim 9, wherein the bit timing symmetrization component is configured to transmit a recessive bit that followed a previously transmitted dominant bit before the start of the next bit time.

### Claim 15 (depends on 9)

The bus interface of claim 9, wherein the bit timing symmetrization component is configured to delay a dominant bit that followed a previously transmitted recessive bit by a configurable amount of time.

### Claim 16 (depends on 9)

The bus interface of claim 9, wherein the bus system is a controlled area network (CAN) bus system.

### Claim 17

A method for receiving and transmitting a bit stream from and to a bus, the method comprising:
receiving a bit stream from the bus;
symmetrizing the bit stream; and
transmitting the bit stream to the bus.

### Claim 18 (depends on 17)

The method of claim 17, further comprising delaying an input signal received from the bit stream to improve a bit timing of the bit stream.

### Claim 19 (depends on 18)

The method of claim 18, wherein the input delay is for a recessive to dominant edge for a given received bit stream.

### Claim 20 (depends on 17)

The method of claim 17, wherein the symmetrizing of the bit stream is performed within a bit timing logic component and the received delayed input signal is delayed within the bit timing logic component.

### Claim 21 (depends on 17)

The method of claim 17, wherein symmetrizing comprises transmitting a recessive bit that followed a previously transmitted dominant bit before the start of the next bit time.

### Claim 22 (depends on 17)

The method of claim 17, wherein symmetrizing comprises delaying a dominant bit that followed a previously transmitted recessive bit by a configurable amount of time.

### Claim 23 (depends on 17)

The method of claim 17, wherein the bus system is a controlled area network (CAN) bus system.

### Claim 24

A bus interface for coupling a device to a bus, the bus allowing a plurality of devices to communicate with one another, the bus interface receiving and transmitting a bit stream from and to the bus, the bus interface comprising:
an input delay filter configured to delay an input signal received from the bit stream to improve a bit timing of the bit stream, wherein the delayed input signal is sampled at a sample point; and
a bit timing synchronization module configured to synchronize the bit stream with an original input signal.

### Claim 25 (depends on 24)

The bus interface of claim 24, wherein the input delay filter is configured to delay a recessive to dominant edge for a given received bit stream.

### Claim 26 (depends on 24)

The bus interface of claim 24, wherein the bus system is a controlled area network (CAN) bus system.

### Claim 27

A method for receiving and transmitting a bit stream from and to a bus, the method comprising:
receiving an original input signal from the bus;
delaying the original input signal from the bus; and
sampling the delayed input signal at a sample point for all recessive to dominant edges of the delayed input signal, wherein a bit timing synchronization is performed using the original input signal.

### Claim 28 (depends on 27)

The method of claim 27, wherein the bus system is a controlled area network (CAN) bus system.