# US 2014/0157033 A1 · Reducing power grid noise in a processor while minimizing performance loss

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- Number: US 2014/0157033 A1
- Document ID: US20140157033A1
- Status: Published application
- Kind: A1
- Application number: 13/693,386
- Filed: 2012-12-04
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Lee E. Eisen; Michael S. Floyd; Thomas Strach; Huajun Wen; Tingdong Zhou
- Web page: https://patentgrep.com/patent/US20140157033A1

## CPC

- G06F 9/46: Multiprogramming arrangements
- G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C)
- G06F 1/329: by task scheduling
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F 1/3243: {Power saving in microcontroller unit}
- G06F 11/3024: {where the computing system component is a central processing unit [CPU]}
- G06F 2201/86: Event-based monitoring
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In the management of a processor, logical operation activity is monitored for increases from a low level to a high level during a sampling window across multiple cores sharing a common supply rail, with at least one decoupling capacitor along the common supply rail. Responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, the processor limits the logical operations executed on the cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level. Responsive to the lower activity period ending, the processor gradually decreases the limit on the logical operations to resume normal operations.

## Claims

### Claim at position 1

1-9. (canceled)

### Claim 10

A system, comprising:
a processor operative to monitor for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor;
the processor, responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, operative to limit the logical operations executed on the plurality of cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level; and
the processor, responsive to the lower activity period ending, operative to gradually decrease the limit on the logical operations executed on the plurality of cores to resume normal operations.

### Claim 11 (depends on 10)

The system of claim 10, further comprising:
the processor operative to monitor for the increase in logical operation activity across at least one switching circuit from among a plurality of switching circuits of the processor, wherein each of the plurality of cores comprises a separate selection of the plurality of switching circuits.

### Claim 12 (depends on 10)

The system of claim 10, further comprising:
each of the plurality of processor cores operative to count a number of logical operations of the logical operation activity over three consecutive time windows during the sampling window;
each of the plurality of processor cores operative to compare a counted number of logical operations for each of the thee consecutive time windows with expected levels specifying activity levels of logical operations of the low level, the medium level, and the high level;
each of the plurality of processor cores, responsive to detecting a first time window of the three consecutive time windows set to the low level and a second time window of the three consecutive time windows set to the high level, operative to set a sudden activity flag;
each of the plurality of processor cores, responsive to detecting the first time window set to the low level, the second time window set to the medium level, and a third time window of the three consecutive time windows set the high level, operative to set the sudden activity flag; and the processor, responsive to detecting the sudden activity flag set, operative to detect the increase in activity from the low level to the high level during the sampling window.

### Claim 13 (depends on 10)

The system of claim 10, further comprising:
each of the plurality of processor cores operative to count a number of logical operations of the logical operation activity over three consecutive time windows during the sampling window;
each of the plurality of processor cores operative to compare a counted number of logical operations for each of the thee consecutive time windows with expected levels specifying activity levels of logical operations of the low level, the medium level, and the high level;
each of the plurality of processor cores, responsive to detecting, for each separate processor core of the plurality of processor cores, within a particular core of the plurality of processor cores, at least one of a first time window of the three consecutive time windows set to the low level and a second time window of the three consecutive time windows set to the high level or the first time window set to the low level, the second time window set to the medium level, and a third time window of the three consecutive time windows set to the high level, operative to set a sudden activity flag for the particular processor core;
the processor, responsive to detecting a number of sudden activity flags set by a number of the plurality of processor cores meeting a threshold, operative to detect the increase in activity from the low level to the high level during the sampling window.

### Claim 14 (depends on 10)

The system of claim 10, further comprising:
the processor operative to monitor for the increase in logical operation activity during the sampling window, wherein the sampling window is set to a time period shorter than a package time constant, wherein the package time constant is proportional to the square root of an inductance from the plurality of switching circuits at a chip level of the processor to a package level of the processor multiplied by the capacitance of the plurality of switching circuits on the common supply rail at the chip level of the processor.

### Claim 15 (depends on 10)

The system of claim 10, further comprising:
the processor operative to limit the logical operations executed on the plurality of cores during the lower activity period, wherein the lower activity period is set to a time period shorter than a package time constant, wherein the package time constant is proportional to the square root of an inductance from the plurality of switching circuits at a chip level of the processor to a package level of the processor multiplied by the capacitance of the plurality of switching circuits on the common supply rail at the chip level of the processor.

### Claim 16 (depends on 10)

The system of claim 10, further comprising:
the processor operative to detect the increase in activity on the threshold selection of the plurality of switching circuits by detecting a threshold number of cores of the plurality of cores indicating the selection of switching circuits of each of the threshold number of cores increasing in activity during the sampling window.

### Claim 17 (depends on 10)

The system of claim 10, further comprising:
the processor operative to decrease the limit on the logical operations from a level of activity on the plurality of switching circuits from a medium level of activity to a high level of activity, wherein during the lower activity period, the limit on the logical operations is set to the level of activity above the low level of activity and below the medium level of activity.

### Claim 18 (depends on 10)

The system of claim 10, further comprising:
the processor operative to monitor for the increase in logical operation activity from the low level to the high level on the processor comprising a plurality of circuits along the common supply rail, wherein the plurality of circuits comprise at least one decoupling capacitor, wherein a voltage droop is triggered in proportion to a change in current increase caused by switching on the plurality of switching circuits multiplied by the square root of an inductance from the plurality of switching circuits on a chip level of the processor to a package level of the processor divided by a capacitance of the plurality of switching circuits.

### Claim 19

A computer program product for managing a processor, the computer program product comprising a computer readable storage medium having program code embodied therewith, the program code executable by a processor to:
monitor for an increase in logical operation activity from a low level to a high level during a sampling window across a plurality of cores sharing a common supply rail of the processor;
responsive to detecting the increase in logical operation activity from the low level to the high level during the sampling window, limit the logical operations executed on the plurality of cores during a lower activity period to a level of logical operations set between the low level and a medium level, where the medium level is an amount between the low level and the high level; and
responsive to the lower activity period ending, gradually decrease the limit on the logical operations executed on the plurality of cores to resume normal operations.

### Claim 20 (depends on 19)

The computer program product of claim 19, further comprising the program code
executable by the processor to:
monitor for the increase in logical operation activity across at least one switching circuit from among a plurality of switching circuits of the processor, wherein each of the plurality of cores comprises a separate selection of the plurality of switching circuits.