# US 2014/0157030 A1 · Systems having a maximum sleep mode and method of operating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0157030 A1 - Document ID: US20140157030A1 - Status: Published application - Kind: A1 - Application number: 14/091,912 - Filed: 2013-11-27 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Samsung Electronics Co., Ltd. - Inventors: Young-Jin PARK; Won-Seok LEE; Il-Guy JUNG - Web page: https://patentgrep.com/patent/US20140157030A1 ## CPC - G06F 1/3275: {Power saving in memory, e.g. RAM, cache} - G06F 1/3209: Monitoring remote activity, e.g. over telephone lines or network connections - G06F 1/3225: of memory devices - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 2212/1028: Power efficiency - G06F 2212/7203: Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks - G06F 2212/7206: Reconfiguration of flash memory system - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - Y02D 30/50: in wire-line communication networks, e.g. low power modes or reduced link rate - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A main memory system includes a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory system being configured such that, when entering a sleep mode, the memory device reads a portion of data stored in the first memory device to store the read data in the second memory device, and, after the portion of data is read, the first memory device and the second memory device are powered off. ## Claims ### Claim 1 A main memory system comprising: a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory system being configured such that, when entering a sleep mode, the memory device reads a portion of data stored in the first memory device to store the read data in the second memory device, and, after the portion of data is read, the first memory device and the second memory device are powered off ### Claim 2 (depends on 1) The main memory system of claim 1, wherein the first memory device includes a dynamic random access memory (DRAM) and the second memory device includes a spin-transfer torque magneto-resistive random access memory (STT-MRAM). ### Claim 3 (depends on 1) The main memory system of claim 1, wherein the main memory device further includes a data transfer manager configured to store data in the second memory device by transferring data stored in the first memory device to the second memory device. ### Claim 4 (depends on 1) The main memory system of claim 1, wherein the main memory system is configured such that when a transmission signal is received from an external device, the second memory device is activated to store data of the transmission signal and then the second memory device is powered off. ### Claim 5 A computer system comprising: a call processor configured to run a realtime operating system; an application processor configured to run a general purpose operating system; and a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the main memory device configured to store data for operations of the call processor and the application processor, and configured to, when entering a high-level sleep mode, read a portion of data stored in the first memory device to store the read data in the second memory device, and then the first memory device and the second memory device are powered off. ### Claim 6 (depends on 5) The computer system of claim 5, wherein the second memory device includes a spin-transfer torque magneto-resistive random access memory (STT-MRAM). ### Claim 7 (depends on 5) The computer system of claim 5, wherein the application processor includes a memory controller configured to control the first memory device and the second memory device. ### Claim 8 (depends on 5) The computer system of claim 5, wherein the call processor includes a memory controller configured to control the second memory device. ### Claim 9 (depends on 5) The computer system of claim 5, wherein the computer system is configured such that when a transmission signal is received from an external device during the high-level sleep mode, the high-level sleep mode is maintained until a wake-up signal is activated. ### Claim 10 (depends on 9) The computer system of claim 9, wherein the transmission signal includes at least one of a text message signal, a call signal and a push message signal. ### Claim 11 (depends on 9) The computer system of claim 9, wherein the computer system is configured such that when the call processor receives the transmission signal from the external device during the high-level sleep mode, the second memory device is activated to store data of the transmission signal and then the second memory device is powered off. ### Claim 12 (depends on 9) The computer system of claim 9, wherein the computer system is configured such that when the call processor receives a call signal from the external device during the high-level sleep mode and the wake-up signal is not activated until the call signal expires, the second memory device is activated to store a call record identifying the call signal and then the second memory device is powered off. ### Claim 13 (depends on 5) The computer system of claim 5, wherein the computer system is configured such that when entering the high-level sleep mode, powers supplied to the call processor and the application processor are reduced. ### Claim 14 (depends on 13) The computer system of claim 13, further comprising: a push notification controller configured to count a reference time interval during the high-level sleep mode to activate the call processor periodically in accordance with the reference time interval. ### Claim 15 (depends on 14) The computer system of claim 14, wherein the computer system is configured such that when the push notification controller activates the call processor, the call processor receives all of push messages transmitted during the predetermined time interval and stores the push messages in the second memory device, and, after the push messages are received and stored by the call processor, the call processor and the second memory device are powered off. ### Claim 16 (depends on 15) The computer system of claim 15, wherein the second memory device includes a queue block, and the computer system is configured such that the push messages are stored in the queue block, and, during the high-level sleep mode, the queue block is activated to receive the push messages while neither the rest of the second memory nor the first memory are activated. ### Claim 17 (depends on 5) The computer system of claim 5, wherein the computer system is configured such that the high-level sleep mode corresponds to a state in which the application processor and the main memory device are powered off. ### Claim 18 (depends on 5) The computer system of claim 5, wherein the computer system is configured such that when the computer system does not receive a signal from an external device for a set time interval in a first sleep mode, the computer system enters the high-level sleep mode from the first sleep mode. ### Claim 19 (depends on 18) The computer system of claim 18, wherein the computer system is configured such that set time interval is configurable by a user. ### Claim 20 (depends on 5) The computer system of claim 5, wherein when the computer system receives an input signal of a user in a normal mode, the computer system enters the high-level sleep mode from the normal mode, the normal mode being a mode in which power levels of the application processor and the main memory are not reduced. ### Claim 21 A computer system comprising: a call processor configured to drive a realtime operating system; an application processor configured to drive a general purpose operating system; a push notification controller configured to count a reference time interval during a sleep mode to activate the call processor periodically in accordance with the reference time interval; and a main memory device configured to store data for operations of the call processor and the application processor, the computer system being configured such that the main memory device is powered off during the sleep mode and only a portion of the main memory device is activated when the computer system receives a transmission signal from an external device during the sleep mode. ### Claim 22 (depends on 21) The computer system of claim 21, wherein the main memory device includes a queue block, the computer system is configured such that push messages are stored in the queue block and, during the high-level sleep mode, the queue block is activated to receive the push messages while the rest of the main memory is not activated. ### Claim 23 A method of operating a system including a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory, the method comprising: reading a portion of data stored in the first memory device in response to a sleep mode signal; storing the read data in the second memory device; entering a sleep mode by powering off the first memory device and the second memory device after the read data are stored in the second memory device; receiving a transmission signal from an external device; and maintaining the sleep mode after receiving the transmission signal. ### Claim 24 (depends on 23) The method of claim 23, wherein the first memory device includes a dynamic random access memory (DRAM) and the second memory device includes a spin-transfer torque magneto-resistive random access memory (STT-MRAM). ### Claim 25 (depends on 23) The method of claim 23, wherein the transmission signal includes at least one of a text message signal, a call signal and a push message signal. ### Claim 26 (depends on 23) The method of claim 23, further comprising: receiving the transmission signal through a call processor; activating at least a portion of the second memory device to store data of the transmission signal; and powering off the second memory device after storing the data of the transmission signal. ### Claim 27 (depends on 23) The method of claim 23, further comprising: when the transmission signal is a call signal, receiving the transmission signal through a call processor; when the call signal expires without a wake-up signal being activated, activating at least a portion of the second memory device and storing a call record identifying the call signal; and powering off the second memory device after storing the call record. ### Claim 28 (depends on 23) The method of claim 23, further comprising: reducing powers supplied to a call processor and an application processor of the system when entering the sleep mode. ### Claim 29 (depends on 28) The method of claim 28, further comprising: counting a reference time interval during the sleep mode using a push notification controller; periodically activating a queue block in the second memory device and the call processor, in accordance with the reference time interval; when the push notification controller activates the call processor, receiving push messages transmitted during the reference time interval; storing the push messages in the queue block; and powering off the call processor and the queue block after the push messages are stored. ### Claim 30 A computing system comprising: a main memory device including a first memory device implemented with a volatile memory and a second memory device implemented with a non-volatile memory; and a power management unit configured to control a supply of power to the main memory device, the computing system being configured such that, when the main memory device enters a sleep mode, the main memory device reads data stored in the first memory device, the main memory stores the read data in the second memory device, and after the read data is stored in the second memory device, the power management unit powers off the first memory device and the second memory device.