# US 2014/0157022 A1 · Electronic device and method for reducing cpu power consumption

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- Number: US 2014/0157022 A1
- Document ID: US20140157022A1
- Status: Published application
- Kind: A1
- Application number: 13/958,650
- Filed: 2013-08-05
- Published: 2014-06-05
- Earliest claimed: 2012-12-04
- Assignees: Hon Hai Precision Industry Co., Ltd.; HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
- Applicants: Hon Hai Precision Industry Co., Ltd.; HONG FU JIN PRECISION INDUSTRY (ShenZhen) CO., LTD.
- Inventors: YA-GUO WANG; CHUN-CHING CHEN
- Web page: https://patentgrep.com/patent/US20140157022A1

## CPC

- G06F 1/324: by lowering clock frequency
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

An electronic device includes a processing system, a storage unit for storing a table, an input unit for generating instruction in response to the operations of the user, and an actuating unit for generating an interrupt in response to the instructions to request the processing system to execute the instructions to perform desired functions. The table recording a relationship between an occupancy and a desired operating speed of the processing system. When the processing system is requested to execute instructions, the processing system calculates the occupancy and adjusts operating speed according to the calculated occupancy and the table. A method for reducing CPU power consumption is also provided.

## Claims

### Claim 1

An electronic device comprising;
a processing system;
a storage unit for storing a table, wherein the table recording a relationship between an occupancy and an operating speed of the processing system;
an input unit for generating instruction in response to user's operations; and
an actuating unit for generating an interrupt in response to the instructions to request the processing system to execute the instructions to perform desired functions;
wherein when the processing system is requested to execute instructions, the processing system calculates the occupancy and adjusts operating speed thereof according to the calculated occupancy and the table.

### Claim 2 (depends on 1)

The electronic device of claim 1, wherein the processing system comprises at least one independent central processing unit and a cache; the central processing unit accesses the instructions and/or data from the cache to achieve high speed.

### Claim 3 (depends on 2)

The electronic device of claim 2, wherein the processing system adjusts the operating speed by changing the data exchange rate between the central processing unit and the cache.

### Claim 4 (depends on 1)

The electronic device of claim 1, wherein the processing system is an embedded processing system.

### Claim 5

A method for reducing CPU power consumption applied in an electronic device comprising a processing system, the method comprising:
providing a table for recording a relationship between the occupancy and desired operating speed of the processing system;
generating instructions in response to user's operations;
generating an interrupt to request the processing system to execute the instructions to perform desired functions in response to the instructions; and
calculating the occupancy and adjusting operating speed according to the calculated occupancy and the table.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the processing system comprises at least one independent central processing unit and a cache; the central processing unit accesses the instructions and/or data from the cache to achieve high speed.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the processing system adjusts the operating speed by changing the data exchange rate between the central processing unit and the cache.

### Claim 8 (depends on 5)

The method of claim 5, wherein the processing system is embedded processing system.