# US 2014/0157021 A1 · Enforcing a power consumption duty cycle in a processor

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- Number: US 2014/0157021 A1
- Document ID: US20140157021A1
- Status: Published application
- Kind: A1
- Application number: 13/997,295
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Intel Corporation
- Inventors: Ankush Varma; Krishnakanth Sistla; Martin T. Rowland; Brian J. Griffith; Viktor D. Vogman; Joseph R. Doucette; Eric J. Dehaemer; Vivek Garg; Chris Poirier; Jeremy J. Shrall; Avinash N. Ananthakrishnan; Stephen H. Gunther
- Web page: https://patentgrep.com/patent/US20140157021A1

## CPC

- G06F 1/3234: Power saving characterised by the action undertaken
- G06F 1/324: by lowering clock frequency
- G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)}
- G06F 8/4432: {Reducing the energy consumption}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
a plurality of cores each to independently execute instructions; and
a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor, the PCU including a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the power excursion control logic is further to limit the power consumption level from being above the defined power limit for more than an excursion duration, a value of the excursion duration stored in a first configuration storage of the processor.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the defined power limit is stored in a second configuration storage of the processor, the defined power limit settable by an original equipment manufacturer (OEM) of a system including the processor.

### Claim 4 (depends on 3)

The processor of claim 3, further comprising a third configuration storage to store a maximum excursion duration, the maximum excursion duration corresponding to a maximum duration for which the processor can operate at a maximum power excursion, wherein the power excursion control logic is to limit the power consumption level from being at the maximum power excursion for longer than the maximum excursion duration.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the power excursion control logic is to obtain the power consumption level from a power detector of the processor, and when the power consumption level is greater than the defined power level, to reduce a frequency limit at which the processor is to operate.

### Claim 6 (depends on 5)

The processor of claim 5, wherein the frequency limit reduction is by a step value when the power consumption level is greater than the defined power limit and less than a second power limit and by a first value greater than the step value when the power consumption level is at the second power limit, the second power limit greater than the defined power limit.

### Claim 7 (depends on 5)

The processor of claim 5, wherein the power excursion control logic is to further update a hold time for which the frequency limit is to be maintained, when the power consumption level is greater than the defined power limit.

### Claim 8 (depends on 7)

The processor of claim 7, wherein the power excursion control logic is to increment the hold time when the power consumption level is greater than the defined power limit and to decrement the hold time during each evaluation interval.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the power excursion control logic is to increase the frequency limit after the hold time is completed.

### Claim 10 (depends on 5)

The processor of claim 5, wherein the PCU is to prevent a software request for an increased performance level from being executed when an operating frequency for the increased performance level is greater than the frequency limit.

### Claim 11

A method comprising:
determining, in a power control unit (PCU) of a processor, whether a power consumption level of the processor is greater than a defined power limit for the processor; and
if so, enforcing a duty cycle so that the power consumption level exceeds the defined power limit for no more than the duty cycle.

### Claim 12 (depends on 11)

The method of claim 11, wherein enforcing the duty cycle comprises reducing a frequency limit to a first value if a number of consecutive determinations of the power consumption level greater than the defined power limit has occurred.

### Claim 13 (depends on 11)

The method of claim 11, wherein enforcing the duty cycle comprises reducing a frequency limit by a step value.

### Claim 14 (depends on 11)

The method of claim 11, further comprising adjusting a hold time by a minimum hold time value.

### Claim 15 (depends on 14)

The method of claim 14, further comprising decrementing the hold time iteratively until the hold time is completed.

### Claim 16 (depends on 15)

The method of claim 15, further comprising thereafter enabling the power consumption limit to exceed the defined power limit.

### Claim 17 (depends on 14)

The method of claim 14, further comprising incrementing the hold time iteratively until the power consumption limit is less than the defined power limit.

### Claim 18

A system comprising:
a multicore processor comprising:
a plurality of cores each to independently execute instructions;
a plurality of graphics engines each to independently perform graphics operations; and
a power control unit (PCU) coupled to the plurality of cores to control power consumption of the multicore processor, the PCU including a control logic to allow a power consumption level of the multicore processor to be above a defined power limit for a portion of an operating period, the portion corresponding to a duty cycle value stored in a configuration storage of the multicore processor;
a power supply unit coupled to the multicore processor to provide a regulated voltage to the multicore processor; and
a dynamic random access memory (DRAM) coupled to the multicore processor.

### Claim 19 (depends on 18)

The system of claim 18, wherein the multicore processor includes a storage to store a frequency limit value corresponding to a maximum allowed operating frequency for the multicore processor, to store a first excursion value corresponding to a first duration for which the multicore processor is allowed to be above the defined power limit, and to store a second excursion value corresponding to a second duration for which the multicore processor is allowed to be at a maximum power excursion above the defined power limit, the second excursion value less than the first excursion value.

### Claim 20 (depends on 19)

The system of claim 19, wherein the PCU is to prevent the multicore processor from operating at an operating frequency greater than the frequency limit value, wherein the control logic is to enforce the duty cycle value by reduction of the frequency limit value to a first value if a threshold number of consecutive determinations of the power consumption level greater than the defined power limit has occurred.

### Claim 21 (depends on 19)

The system of claim 19, wherein the PCU is to prevent the power consumption level from exceeding the defined power limit for longer than the first excursion value, and to prevent the processor from operating at the maximum power excursion for longer than the second excursion value.

### Claim 22 (depends on 18)

The system of claim 18, wherein the power supply unit comprises a battery to provide the regulated voltage to the multicore processor.

### Claim 23

(canceled)

### Claim 24

(canceled)

### Claim 25

(canceled)

### Claim 26

(canceled)