# US 2014/0156984 A1 · Multi-processor systems and booting methods thereof

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- Number: US 2014/0156984 A1
- Document ID: US20140156984A1
- Status: Published application
- Kind: A1
- Application number: 14/174,151
- Filed: 2014-02-06
- Published: 2014-06-05
- Earliest claimed: 2006-02-15
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Jong-Ho Roh; Min-Soo Lim
- Web page: https://patentgrep.com/patent/US20140156984A1

## CPC

- G06F 9/4405: {Initialisation of multiprocessor systems}
- G06F 15/177: Initialisation or configuration control {(processor initialisation G06F9/4405)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Multi-processor systems and methods thereof are provided. In an example, the multi-processor system may include a boot memory including a plurality of boot codes, each of the plurality of boot codes configured to facilitate an initialization process at one of a plurality of intellectual property (IP) blocks, each of the plurality of IP blocks having shared access to the boot memory. In another example, the multi-processor system may receive, from a first processor, a request to provide one of a plurality of boot codes from a boot memory, the received request sent in response to a system initializing signal, may read the requested boot code from the boot memory and may transfer, from a second processor, the read boot code to the first processor.

## Claims

### Claim 1

(canceled)

### Claim 2

A processing device, comprising:
a processor and an interface buffer, the processor configured to connect to a system bus of a multi-processor system and to activate the interface buffer, the interface buffer configured to connect to a local bus to receive a first boot code upon receipt of an activating signal from the processor, wherein the processor is further configured to activate the interface buffer to access a second boot code via the local bus upon receipt of an instruction from a processor of another processing device and to transfer the second boot code to the second processing device via the system bus.

### Claim 3 (depends on 2)

The processing device of claim 2, wherein the processor includes the interface buffer.

### Claim 4 (depends on 2)

The processing device of claim 2, wherein a system memory is included in the another processing device and the system memory is configured to store the second boot code.

### Claim 5 (depends on 2)

The processing device of claim 2, further comprising a host interface to communicate with the another processing device

### Claim 6 (depends on 2)

The processing device of claim 2, wherein the instruction is configured to activate the interface buffer.

### Claim 7 (depends on 2)

The processing device of claim 2, wherein the first boot code and the second boot code are stored in a boot memory.

### Claim 8 (depends on 7)

The processing device of claim 7, wherein the boot memory is connected to the local bus.

### Claim 9 (depends on 2)

The processing device of claim 2, wherein a system memory is included in the another processing device and the system memory is configured to store the boot code.

### Claim 10 (depends on 2)

The processing device of claim 2, further comprising a host interface to communicate with the another processing device.

### Claim 11

A multi-processor system, comprising:
A first intellectual property (IP) block including a first processor and a second IP block including a second processor, each of the first processor or the second processor configured to connect to a system bus to receive a corresponding first boot code or a corresponding second boot code upon issuing an instruction configured to retrieve the first boot code or the second boot code from a shared boot memory.

### Claim 12 (depends on 11)

The system according to claim 11, wherein the shared boot memory is included in either the first IP block or the second IP block.

### Claim 13 (depends on 11)

The system according to claim 11, wherein either the first IP block or the second IP block includes an interface buffer.

### Claim 14 (depends on 11)

The system according to claim 11, wherein the shared boot memory is a NOR flash.

### Claim 15 (depends on 11)

The system according to claim 11, wherein the shared boot memory is included in a third IP block connected to the system bus.

### Claim 16 (depends on 15)

The system according to claim 15, wherein the third IP block includes a third processor and an interface buffer.

### Claim 17 (depends on 11)

The system according to claim 11, wherein the instruction is further configured to activate an interface buffer.

### Claim 18

A multi-processor system, comprising:
A first intellectual property (IP) block including a first processor; and
a second IP block including a second processor, a boot memory storing a plurality of boot codes, and an interface buffer configured to store a boot code read from the boot memory, wherein the second processor is configured to read a boot code from the boot memory corresponding to the second IP block to initialize the second IP block, wherein
the first IP block and the second IP block are connected via a system bus, and the first IP block is configured to issue an instruction to effect retrieval of a boot code corresponding to the first IP block from the boot memory via the interface buffer.

### Claim 19 (depends on 18)

The system according to claim 18, wherein the boot code corresponding to the first IP block is received by the first IP block via the system bus.

### Claim 20 (depends on 18)

The system according to claim 18, wherein the instruction is configured to activate the interface buffer.

### Claim 21 (depends on 18)

The system according to claim 18, further including a third IP block connected to the first and second IP blocks via one of a system bus or a local bus, the third IP block is configured to issue an instruction to effect retrieval of a boot code corresponding to the third IP block from the boot memory via the interface buffer.