# US 2014/0156978 A1 · Detecting and Filtering Biased Branches in Global Branch History

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- Number: US 2014/0156978 A1
- Document ID: US20140156978A1
- Status: Published application
- Kind: A1
- Application number: 13/691,049
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Inventors: Muawya M. AL-OTOOM; Paul CAPRIOLI; Jeffrey J. COOK
- Web page: https://patentgrep.com/patent/US20140156978A1

## CPC

- G06F 9/3844: {using dynamic branch prediction, e.g. using branch history tables}
- G06F 9/3848: {using hybrid branch prediction, e.g. selection between prediction techniques}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A processor includes an instruction pipeline for executing instructions including a branching instruction, a counter for counting times that the branching instruction is taken, a register for storing a global branch history as a function of a value of the counter, and a branch prediction unit for predicting branching based on the global branch history.

## Claims

### Claim 1

A processor, comprising:
an instruction pipeline to execute instructions including a branching instruction;
a counter to count a number of times that the branching instruction is taken;
a register to store a global branch history as a function of a value of the counter; and
a branch prediction unit to predict branching based on the global branch history.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the counter is start counting with an initial value.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the counter has a limited length.

### Claim 4 (depends on 3)

The processor of claim 3, wherein each time the branching instruction is taken, the value of the counter is to be incremented by one, and each time the branching instruction is not taken, the value of the counter is decremented by one.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the branching instruction is considered biased if the value of the counter equals one of a maximum value and a minimum value of the counter.

### Claim 6 (depends on 4)

The processor of claim 4, wherein the branching instruction is biased if the value of the counter is outside a range.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the global branch history is to record results of the branching instruction only if the branching instruction is not biased.

### Claim 8 (depends on 5)

The processor of claim 5, wherein the global branch history is to record results of the branching instruction only if the branching instruction is not biased.

### Claim 9 (depends on 5)

The processor of claim 5, wherein the global branch history is not to record results of the branching instruction if the branching instruction is biased.

### Claim 10 (depends on 1)

The processor of claim 1, further comprising a controller that is coupled to the counter and the register for determining whether the branching instruction is biased based on the value of the counter.

### Claim 11

A processor, comprising:
a plurality of processing cores, each processing core including:
an instruction pipeline to execute instructions including a plurality of branching instructions;
a first register including a plurality of counters, each of the plurality of counters to count respective times that the plurality of branching instructions are taken or not;
a second register to store a global branch history as a function of a value of the plurality of counters; and
a branch prediction unit to predict branching based on the global branch history.

### Claim 12 (depends on 11)

The processor of claim 11, wherein each of the plurality of counters has a limited length.

### Claim 13 (depends on 11)

The processor of claim 11, wherein each of the plurality of counters is to start with an initial value, and wherein each time the corresponding branching instruction is taken, the value of the corresponding counter is incremented by one, and each time the corresponding branching instruction is not taken, the value of the corresponding counter is decremented by one.

### Claim 14 (depends on 13)

The processor of claim 13, wherein the corresponding branching instruction is considered biased if the value of the corresponding counter equals one of a maximum value and a minimum value of the counter.

### Claim 15 (depends on 13)

The processor of claim 13, wherein the corresponding branching instruction is biased if the value of the counter is outside a range.

### Claim 16 (depends on 15)

The processor of claim 15, wherein the global branch history is to record results of the corresponding branching instruction only if the corresponding branching instruction is not biased.

### Claim 17 (depends on 14)

The processor of claim 14, wherein the global branch history is to record results of the branching instruction only if the branching instruction is not biased.

### Claim 18

A system, comprising:
a processor;
a memory to store instructions to be executed by the processor;
the processor including
an instruction pipeline to execute instructions including a branching instruction;
a first register including bits as bias indicators to be set by an operating system, each bias indicator indicating whether a branching instruction is biased or not;
a second register to store a global branch history that is recorded as a function of the bias indicators; and
a branch prediction unit to predict branching based on the global branch history.

### Claim 19 (depends on 18)

The system of claim 18, wherein the operating system is to determine whether the branching instruction is biased or not, and wherein the branching instruction is biased if a ratio of the branching instruction being taken versus not taken is higher than a pre-specified threshold.

### Claim 20 (depends on 19)

The system of claim 19, wherein a result of the branching instruction is to be recorded in the global branch history only if the corresponding bias indicator does not indicate a bias status.

### Claim 21 (depends on 18)

The system of claim 18, wherein the bias indicators are further to be set by at least one of dedicated hardware circuitry, firmware layer, and compiler.

### Claim 22

A method comprising:
executing instructions in a processor including a branching instruction;
counting with a counter a number of times that the branching instruction is taken during execution;
storing in a register a global branch history as a function of a value of the counter; and
predicting branching with a branch prediction unit based on the global branch history.

### Claim 23 (depends on 22)

The method of claim 22, further comprising wherein, incrementing the value of the counter by one each time the branching instruction is taken, and decrementing the value of the counter by one each time the branching instruction is not taken.

### Claim 24 (depends on 23)

The method of claim 23, wherein the branching instruction is considered biased if the value of the counter equals one of a maximum value and a minimum value of the counter.

### Claim 25 (depends on 24)

The method of claim 24, further comprising recording results of the branching instruction in the global branch history records results only if the branching instruction is not biased.