# US 2014/0156975 A1 · Redundant Threading for Improved Reliability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156975 A1 - Document ID: US20140156975A1 - Status: Published application - Kind: A1 - Application number: 13/690,841 - Filed: 2012-11-30 - Published: 2014-06-05 - Earliest claimed: 2012-11-30 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Vilas SRIDHARAN; James M. O'Connor; Steven K. Reinhardt; Nuwan S. Jayasena; Michael J. Schulte; Dean A. Liberty - Web page: https://patentgrep.com/patent/US20140156975A1 ## CPC - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F 9/3851: {from multiple instruction streams, e.g. multistreaming} - G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]} - G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel} - G06F 11/1641: {where the comparison is not performed by the redundant processing components} - G06F 11/1691: {using a quantum} - G06F 11/1695: {which are operating with time diversity} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In some embodiments, a method for improving reliability in a processor is provided. The method can include replicating input data for first and second lanes of a processor, the first and second lanes being located in a same cluster of the processor and the first and second lanes each generating a respective value associated with an instruction to be executed in the respective lane, and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match. ## Claims ### Claim 1 A method, comprising: replicating input data for first and second lanes of a processor, wherein the first and second lanes are located in a same cluster of the processor and wherein the first and second lanes each generate a respective value associated with an instruction to be executed in the respective lane; and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match. ### Claim 2 (depends on 1) The method of claim 1, wherein providing an indication comprises: incrementing a counter. ### Claim 3 (depends on 1) The method of claim 1, wherein each instruction comprises a store instruction. ### Claim 4 (depends on 1) The method of claim 1, wherein providing the indication comprises: raising an exception. ### Claim 5 (depends on 1) The method of claim 1, further comprising: replicating the input data for a third lane of the cluster, wherein providing the indication comprises completing the instruction responsive to a determination that two of the values generated by the first, second, and third lanes match. ### Claim 6 (depends on 5) The method of claim 5, wherein completing the instruction comprises: completing the instruction in a lane of the first, second, and third lanes whose value is equal to the majority value. ### Claim 7 (depends on 1) The method of claim 1, wherein the replicating comprises: providing identical work-item identifiers to each of the first and second lanes. ### Claim 8 (depends on 1) The method of claim 1, wherein each of the instructions is included in a first wavefront spanning the first and second lanes, further comprising: generating at least one mirrored wavefront having state identical to state of the first wavefront, wherein each of the first wavefront and the at least one wavefront generates a second value associated with a second instruction to be executed therein; responsive to a determination that the second generated values do not match, providing an indication that the second generated values do not match. ### Claim 9 (depends on 8) The method of claim 8, wherein providing the indication that the second generated values do not match comprises: raising an exception. ### Claim 10 (depends on 8) The method of claim 8, wherein the at least one wavefront comprises at least two wavefronts, further comprising: completing the second instruction if a majority value of second generated values is determinable. ### Claim 11 (depends on 10) The method of claim 10, wherein the completing comprises: completing the instruction in a wavefront whose respective second generated value is equal to the majority value. ### Claim 12 (depends on 1) The method of claim 1, wherein comparing comprises: executing at least one instruction that effects a comparison of the generated values. ### Claim 13 (depends on 1) The method of claim 1, wherein the replicating and the comparing occur in response to a request for an application for high reliability. ### Claim 14 (depends on 1) The method of claim 1, wherein the value is a memory address or data to be written to the memory address. ### Claim 15 A method, comprising: generating at least one mirrored wavefront having state identical to state of a first wavefront, wherein each of the first wavefront and the at least one wavefront generates a value associated with an instruction to be executed therein; and responsive to a determination that the generated values do not match, providing an indication that the generated values do not match. ### Claim 16 (depends on 15) The method of claim 15, wherein providing the indication comprises: raising an exception. ### Claim 17 (depends on 15) The method of claim 15, wherein the at least one wavefront comprises at least two wavefronts and wherein the providing an indication comprises: completing the instruction if a majority value of the generated values is determinable. ### Claim 18 A system, comprising: a scheduler configured to replicate input data for first and second lanes of a processor, wherein the first and second lanes are located in the same cluster of the processor and wherein each of the first and second lanes generates a respective value associated with an instruction to be executed in the respective lane; and a comparator configured to compare the generated values. ### Claim 19 (depends on 18) The system of claim 18, wherein the comparator is configured to raise an exception if the values do not match. ### Claim 20 A system for improving reliability in a processor, comprising: a scheduler configured to generate at least one mirrored wavefront having state identical to state of a first wavefront, wherein each of the first wavefront and the at least one wavefront generates a value associated with an instruction to be executed therein; and a comparator configured to compare the generated values.