# US 2014/0156973 A1 · Processor and control method of processor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156973 A1 - Document ID: US20140156973A1 - Status: Published application - Kind: A1 - Application number: 14/060,050 - Filed: 2013-10-22 - Published: 2014-06-05 - Earliest claimed: 2012-12-03 - Assignees: Fujitsu Limited - Applicants: Fujitsu Limited - Inventors: Takashi SUZUKI - Web page: https://patentgrep.com/patent/US20140156973A1 ## CPC - G06F 9/322: {for non-sequential address} - G06F 9/323: {for indirect branch instructions} - G06F 9/3806: {using address prediction, e.g. return stack, branch history buffer} - G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A processor comprises an instruction fetch unit to acquire an instruction from an instruction address defined as an instruction storage source at a fetching stage of the processor repeating an instruction process including the fetching stage of fetching the instruction and an execution stage of executing the instruction, an associative relation storage unit to register an associative relation between a high-order bit field of the instruction address of the instruction undergoing the instruction process and high-order address information into which the high-order bit field of the instruction address is encoded, an encoding unit to encode the high-order bit field contained in the instruction address into the high-order address information on the basis of the associative relation and a decoding unit to decode the high-order bit field from the high-order address information and the associative relation. ## Claims ### Claim 1 A processor comprising: an instruction fetch unit to fetch an instruction from an instruction address defined as an instruction storage source at a fetching stage of the processor repeating an instruction process including the fetching stage of fetching the instruction and an execution stage of executing the instruction; an associative relation storage unit to register an associative relation between a high-order bit field of the instruction address of the instruction undergoing the instruction process and high-order address information into which the high-order bit field of the instruction address is encoded; an encoding unit to encode the high-order bit field contained in the instruction address into the high-order address information on the basis of the associative relation; and a decoding unit to decode the high-order bit field from the high-order address information and the associative relation. ### Claim 2 (depends on 1) The processor according to claim 1, further comprising a switchover determining unit, in a case where the instruction undergoing the instruction process is a branch instruction, to cancel a branch prediction for the branch instruction when the associative relation with respect to at least one of a branch destination address of the branch instruction and a branch source address of the branch instruction is not registered in the associative relation storage unit and the branch instruction branches off to a branch destination in a range in which the high-order address changes, and to update the associative relation when the associative relation with respect to the branch destination address of the branch instruction is not registered in the associative relation storage unit and the branch instruction branches off to the branch destination in the range in which the high-order address changes. ### Claim 3 (depends on 1) The processor according to claim 1, wherein the encoding unit generates a code indicating a not-registered status of the high-order bit field of the instruction address of which the associative relation is not registered. ### Claim 4 (depends on 1) The processor according to claim 1, further comprising a program counter to indicate the instruction address of the instruction fetched by the instruction fetch unit, wherein the decoding unit decodes the high-order bit field from the instruction address indicated by the program counter with respect to the high-order address information of which the associative relation is not registered. ### Claim 5 (depends on 1) The processor according to claim 1, wherein the associative relation storage unit stores the associative relation in the way of being shared between the threads, the processor further comprising a high-order address conversion invalidation signal indicating unit to cause the encoding unit to execute a process which is to be executed when the associative relation of the high-order address is not registered and to cause the decoding unit to execute a process which is to be executed when the associative relation of the high-order address information is not registered during a period till the instruction process is redone from the fetching stage in a second thread when updating the associative relation in a first thread. ### Claim 6 A control method of a processor comprising: fetching an instruction from an instruction address defined as an instruction storage source at a fetching stage of a processor repeating an instruction process including the fetching stage of fetching the instruction and an execution stage of executing the instruction; registering, in an associative relation storage unit, an associative relation between a high-order bit field of the instruction address of the instruction undergoing the instruction process and high-order address information into which the high-order bit field of the instruction address is encoded; encoding the high-order bit field contained in the instruction address into the high-order address information on the basis of the associative relation; decoding the high-order bit field from the high-order address information on the basis of the associative relation; and predicting whether an instruction fetched by the instruction fetch unit is a branch instruction or not on the basis of history information to store the high-order address information and a low-order bit field associated with a branch destination address of the branch instruction undergoing the instruction process.