# US 2014/0156972 A1 · Control Transfer Termination Instructions Of An Instruction Set Architecture (ISA)

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- Number: US 2014/0156972 A1
- Document ID: US20140156972A1
- Status: Published application
- Kind: A1
- Application number: 13/690,221
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Intel Corporation
- Inventors: Vedyvas Shanbhogue; Jason W. Brandt; Uday R. Savagaonkar; Ravi L. Sahita
- Web page: https://patentgrep.com/patent/US20140156972A1

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/3005: {to perform operations for flow control}
- G06F 9/30054: {Unconditional branch instructions}
- G06F 9/30076: {to perform miscellaneous control operations, e.g. NOP}
- G06F 9/323: {for indirect branch instructions}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F 9/3861: {Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00)}
- G06F 21/52: during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow}
- G06F 9/3012: {Organisation of register space, e.g. banked or distributed register file}
- G06F 21/71: to assure secure computing or processing of information
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In an embodiment, the present invention includes a processor having an execution logic to execute instructions and a control transfer termination (CTT) logic coupled to the execution logic. This logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction. Other embodiments are described and claimed.

## Claims

### Claim 1

A processor comprising:
a fetch unit to fetch instructions;
a decode unit to decode the instructions, the decode unit including a control transfer termination (CTT) logic, responsive to a control transfer instruction, to decode the control transfer instruction into a decoded control transfer instruction;
an execution unit to execute decoded instructions; and
a retirement unit to retire the decoded control transfer instruction, wherein the retirement unit is to raise a fault if a next instruction to be retired after the decoded control transfer instruction is not a CTT instruction.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the decode unit is to associate a second state with the decoded control transfer instruction to indicate that the CTT logic is in a wait state.

### Claim 3 (depends on 2)

The processor of claim 2, wherein the decode unit is to associate a first state with a decoded CTT instruction decoded by the decode unit after the control transfer instruction, to indicate that the CTT logic is in an idle state.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the decode unit is to provide the decoded control transfer instruction and the second state to the execution unit.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the retirement unit is to communicate a last retired instruction and a state of the CTT logic associated with the last retired instruction to the decode unit responsive to a misprediction, wherein the decode unit is to update a state of the CTT logic using the communicated state.

### Claim 6 (depends on 3)

The processor of claim 3, wherein the CTT logic is to insert a fault instruction when an instruction decoded after the control transfer instruction is not a CTT instruction.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the retirement unit is to raise the fault responsive to the fault instruction, the fault instruction corresponding to a CTT fault micro-operation.

### Claim 8 (depends on 1)

The processor of claim 1, further comprising a compiler to insert a first CTT instruction as a first instruction in a first subroutine to be called by the control transfer instruction, the control transfer instruction corresponding to a call instruction.

### Claim 9 (depends on 7)

The processor of claim 7, wherein the compiler is to insert a second CTT instruction as a first instruction after the call instruction.

### Claim 10 (depends on 1)

The processor of claim 1, further comprising a configuration register to store a CTT state including an enable field to enable the CTT logic, a tracker field to store a state of the CTT logic, and a suppression field to suppress the CTT logic.

### Claim 11 (depends on 1)

The processor of claim 1, wherein the CTT instruction comprises a multi-byte opcode, the CTT instruction to be executed as a no operation by the execution unit.

### Claim 12 (depends on 1)

The processor of claim 1, wherein the decode unit further comprises a second CTT logic, the CTT logic to operate at a user level and the second CTT logic to operate at a supervisor level.

### Claim 13

A processor comprising:
an execution logic to execute instructions; and
a control transfer termination (CTT) logic coupled to the execution logic, wherein the CTT logic is to cause a CTT fault to be raised if a target instruction of a control transfer instruction is not a CTT instruction.

### Claim 14 (depends on 13)

The processor of claim 13, wherein the processor further comprises a retirement unit, the retirement unit to raise the CTT fault after retirement of the CTT instruction.

### Claim 15 (depends on 13)

The processor of claim 13, wherein the CTT instruction comprises a user-level instruction having a multi-byte opcode.

### Claim 16 (depends on 15)

The processor of claim 15, wherein the CTT instruction is to execute as a no operation in the execution logic.

### Claim 17 (depends on 13)

The processor of claim 13, wherein the processor further comprises a decode unit to decode a CTT suppression instruction to cause the CTT logic to remain in an idle state responsive to a control transfer instruction, to prevent the CTT fault from being raised.

### Claim 18 (depends on 17)

The processor of claim 17, wherein the decode unit is further to decode a CTT suppression removal instruction to cause the CTT logic to transition to a wait state responsive to a control transfer instruction.

### Claim 19

A machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:
decoding a control transfer instruction and decoding a next instruction following the control transfer in a decode unit of a processor;
providing the control transfer instruction and the next instruction to a pipeline of the processor;
retiring the control transfer instruction in a retirement unit of the processor; and
raising a fault via the retirement unit, if the next instruction is not a control transfer termination (CTT) instruction.

### Claim 20 (depends on 19)

The machine-readable medium of claim 19, further comprising instructions that cause the machine to handle the fault and to update a state of a CTT logic of the decode unit.

### Claim 21 (depends on 20)

The machine-readable medium of claim 20, further comprising instructions that cause the CTT logic to transition into a wait state responsive to the control transfer instruction.

### Claim 22 (depends on 21)

The machine-readable medium of claim 21, further comprising instructions that cause the CTT logic to transition into an idle state responsive to the next instruction, wherein the next instruction is a CTT instruction.

### Claim 23 (depends on 19)

The machine-readable medium of claim 19, further comprising instructions that cause the machine to provide a CTT fault instruction to the pipeline when the next instruction is not a CTT instruction.

### Claim 24 (depends on 19)

The machine-readable medium of claim 19, wherein the CTT instruction is inserted via a binary rewriting tool.

### Claim 25

A system comprising:
a processor including a front end unit having a control transfer termination (CTT) logic, an execution logic coupled to the front end unit to execute instructions, and a retirement unit coupled to the execution logic, wherein the retirement unit is to raise a CTT fault when a target instruction of a retired control transfer instruction is not a CTT instruction; and
a dynamic random access memory (DRAM) coupled to the processor.

### Claim 26 (depends on 25)

The system of claim 25, wherein the DRAM includes a program having an image, the image including a first control transfer instruction to call a first library, the first library having a second control transfer instruction to call a second library, wherein the first library is configured to execute CTT instructions and the second library is not configured to execute CTT instructions.

### Claim 27 (depends on 26)

The system of claim 26, wherein the first library includes a first instruction to disable the CTT logic prior to execution of the second control transfer instruction, and a second instruction to enable the CTT logic prior to execution of a return instruction to return to the image.

### Claim 28 (depends on 26)

The system of claim 26, wherein the first library includes a first CTT instruction as a target instruction of the first control transfer instruction, and the image includes a second CTT instruction as a target instruction of a return instruction of the first library.

### Claim 29 (depends on 25)

The system of claim 25, wherein the processor further comprises a decode unit to decode a CTT suppression instruction to cause the CTT logic to remain in an idle state responsive to a second control transfer instruction to prevent the CTT fault from being raised if a target instruction of the second control transfer instruction is not a CTT instruction, and to thereafter decode a CTT suppression removal instruction to cause the CTT logic to transition to a wait state responsive to a third control transfer instruction.

### Claim 30 (depends on 29)

The system of claim 29, wherein the processor further comprises a configuration register to store a CTT state including an enable field to enable the CTT logic and a suppression field to cause the CTT logic to remain in the idle state.