# US 2014/0156969 A1 · Verification of a vector execution unit design

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- Number: US 2014/0156969 A1
- Document ID: US20140156969A1
- Status: Published application
- Kind: A1
- Application number: 14/109,221
- Filed: 2013-12-17
- Published: 2014-06-05
- Earliest claimed: 2012-11-12
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: MAARTEN J. BOERSMA; UDO KRAUTZ; ULRIKE SCHMIDT
- Web page: https://patentgrep.com/patent/US20140156969A1

## CPC

- G06F 9/30: Arrangements for executing machine instructions, e.g. instruction decode (for executing microinstructions G06F9/22)
- G06F 9/3001: {Arithmetic instructions}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 11/16: Error detection or correction of the data by redundancy in hardware
- G06F 11/1629: {Error detection by comparing the output of redundant processing systems}
- G06F 11/1641: {where the comparison is not performed by the redundant processing components}
- G06F 11/2226: {to test ALU}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for verification of a vector execution unit design. The method includes issuing an instruction into a first instance and a second instance of a vector execution unit. The method includes issuing a random operand into a first lane of the first instance of the vector execution unit and into a second lane of the second instance of the vector execution unit. The method further includes receiving results from execution of the instruction and the random operand in both the first and the second instance of the vector execution unit and comparing the received results.

## Claims

### Claim 1

A method for verification of a vector execution unit design, the method comprising the steps of:
issuing an instruction into a first instance of a vector execution unit;
issuing the instruction into a second instance of the vector execution unit;
issuing a random operand into a first lane of the first instance of the vector execution unit;
issuing the random operand into a second lane of the second instance of the vector execution unit;
receiving results from execution of the instruction and the random operand in the first instance of the vector execution unit and results from execution of the instruction and the random operand in the second instance of the vector execution unit; and
comparing the received results.

### Claim 2 (depends on 1)

The method of claim 1, further comprising the steps of:
issuing the instruction and the random operand into at least one different lane in at least one additional instance of the vector execution unit;
receiving results from execution of the instruction and the random operand in the at least one additional instance of the vector execution unit; and
comparing the results from execution of the instruction and the random operand in the at least one additional instance of the vector execution unit to the results from execution of the instruction and the random operand in the first instance of the vector execution unit and results from execution of the instruction and the random operand in the second instance of the vector execution unit.

### Claim 3 (depends on 1)

The method of claim 1, further comprising the step of inputting random operands into unused lanes of the first and the second instance of the vector execution unit.

### Claim 4 (depends on 2)

The method of claim 2, further comprising the step of inputting random operands into unused lanes of the at least one additional instance of the vector execution unit.

### Claim 5 (depends on 1)

The method of claim 1, wherein the step of comparing the received results further comprises one or more computer processors determining whether the results are equal and responsive to determining the results are equal, the one or more computer processors determining the lanes of the vector execution unit are equivalent.

### Claim 6 (depends on 5)

The method of claim 5, wherein the step of determining whether the results are equal further comprises, responsive to determining the results are not equal, generating a trace.