# US 2014/0156962 A1 · Common contiguous memory region optimized virtual machine migration within a workgroup

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- Number: US 2014/0156962 A1
- Document ID: US20140156962A1
- Status: Published application
- Kind: A1
- Application number: 13/690,107
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Eli M. Dow; James P. Gilchrest; Steven K. Schmidt; Jessie Yu
- Web page: https://patentgrep.com/patent/US20140156962A1

## CPC

- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/0647: {Migration mechanisms}
- G06F 3/065: {Replication mechanisms}
- G06F 3/067: {Distributed or networked storage systems, e.g. storage area networks [SAN], network attached storage [NAS]}
- G06F 9/00: Arrangements for program control, e.g. control units (program control for peripheral devices G06F13/10)
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/5016: {the resource being the memory}
- G06F 9/5077: {Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455)}
- G06F 9/5088: {involving task migration}
- G06F 2009/4557: {Distribution of virtual machine instances; Migration and load balancing}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Embodiments of the invention relate to scanning, by a first processor in a work group, a memory associated with the first processor for data. The first processor updates a first data structure to include at least a portion of the data based on the scanning. The first processor transmits a representation of the first data structure to one or more peer processors of the first processor included in the work group using a dedicated link. The first processor receives a representation of a second data structure associated with at least one of the one or more peer processors of the first processor. The first processor updates the first data structure based on the received representation of the second data structure.

## Claims

### Claim at position 1

1-16. (canceled)

### Claim 17

An apparatus comprising:
at least one processing device; and
a storage device having instructions stored thereon that, when executed by the at least one processing device, cause the apparatus to:
scan a memory associated with the apparatus for strings of data,
update a first data structure based on the scan,
transmit a representation of the first data structure to one or more peer processors of the apparatus included in a work group,
receive a representation of a second data structure associated with at least one of the one or more peer processors of the apparatus, and
update the first data structure based on the received representation of the second data structure.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein each of a plurality of entries in the first data structure comprises:
a first indicator, wherein the first indicator indicates whether a full page of the memory is being referenced,
a second indicator, wherein the second indicator indicates a size of a chunk of the memory,
a third indicator, wherein the third indicator indicates the payload of the chunk of the memory,
a fourth indicator, wherein the fourth indicator identifies the apparatus, and
a fifth indicator, wherein the fifth indicator indicates a number of times that the payload is replicated on the apparatus.

### Claim 19 (depends on 17)

The apparatus of claim 17, wherein the instructions, when executed by the at least one processing device, cause the apparatus to:
update the first data structure based on the received representation of the second data structure by generating second strings of data associated with the second data structure.

### Claim 20

A computer program product comprising:
a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising:
computer readable program code configured for:
receiving a request from a virtual machine to migrate the virtual machine from a first processor,
determining a minimum hardware configuration to support the virtual machine responsive to the request,
constructing a list of one or more candidate processors in a work group to migrate the virtual machine to, wherein each of the one more candidate processors supports the minimum hardware configuration,
determining for each of the one or more candidate processors information about shared contiguous memory regions accessible to the candidate processor that is in common to contiguous memory regions accessed by the virtual machine, and
migrating the virtual machine from the first processor to a second processor included in the list of one or more candidate processors based on the determination of the information about shared contiguous memory regions accessible to each of the one or more candidate processors that are in common to contiguous memory regions accessed by the virtual machine.

### Claim 21 (depends on 20)

The computer program product of claim 20, wherein the computer readable program code is further configured for:
migrating the virtual machine from the first processor to the second processor based on determining that a number of contiguous memory regions accessible to the second processor that are in common to contiguous memory regions accessed by the virtual machine is greater than or equal to a number of contiguous memory regions accessible to each of the other one or more candidate processors that are in common to contiguous memory regions accessed by the virtual machine.

### Claim 22 (depends on 20)

The computer program product of claim 20, wherein the computer readable program code is further configured for:
selecting the second processor as a destination for the migration of the virtual machine based on an availability of resources at the second processor, capabilities of the resources at the second processor, a load at the second processor, and an anticipated migration time from the first processor to the second processor.