# US 2014/0156951 A1 · Multicore, multibank, fully concurrent coherence controller

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- Number: US 2014/0156951 A1
- Document ID: US20140156951A1
- Status: Published application
- Kind: A1
- Application number: 14/060,192
- Filed: 2013-10-22
- Published: 2014-06-05
- Earliest claimed: 2012-10-24
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Matthew D. Pierson; Kai Chirca
- Web page: https://patentgrep.com/patent/US20140156951A1

## CPC

- G06F 21/78: to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00)
- G06F 12/0815: Cache consistency protocols
- G06F 12/0828: {with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions}
- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 12/0835: {for main memory peripheral accesses (e.g. I/O or DMA)}
- G06F 12/0842: for multiprocessing or multitasking
- G06F 12/1081: for peripheral access to main memory, e.g. direct memory access [DMA]
- G06F 12/1458: {by checking the subject access rights}
- G06F 12/1491: {in a hierarchical protection system, e.g. privilege levels, memory rings}
- G06F 13/1605: {based on arbitration (arbitration in handling access to a common bus or bus system G06F13/36)}
- G06F 13/1626: {by reordering requests}
- G06F 13/1663: {Access to shared memory}
- G06F 13/287: {Multiplexed DMA (G06F13/30 takes precedence)}
- G06F 13/30: with priority control
- G06F 13/4022: {using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence)}
- G06F 13/42: Bus transfer protocol, e.g. handshake; Synchronisation
- G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories
- H04L 63/0263: {Rule management}
- G06F 2212/1032: Reliability improvement, data loss prevention, degraded operation etc
- G06F 2212/283: Plural cache memories
- G06F 2212/62: Details of cache specific to multiprocessor cache arrangements
- G06F 2212/621: Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

This invention optimizes non-shared accesses and avoids dependencies across coherent endpoints to ensure bandwidth across the system even when sharing. The coherence controller is distributed across all coherent endpoints. The coherence controller for each memory endpoint keeps a state around for each coherent access to ensure the proper ordering of events. The coherence controller of this invention uses First-In-First-Out allocation to ensure full utilization of the resources before stalling and simplicity of implementation. The coherence controller provides Snoop Command/Response ID Allocation per memory endpoint.

## Claims

### Claim 1

An data processing system comprising:
a plurality of processing cores, at least one processing core including cache memory for temporarily storing data;
a plurality of memory endpoints storing data; and
a plurality of coherence controllers, one corresponding to each of said plurality of memory endpoints, each coherence controller ordering memory reads and writes from said plurality of processing cores to maintain coherence in said corresponding memory endpoint.

### Claim 2 (depends on 1)

The data processing system of claim 1, wherein:
each of said plurality of coherence controllers includes
a coherence maintenance address queue having a plurality of entries, each entry storing an address of an access request committed to the shared memory and an assigned ID tag,
an ID allocation block coupled to said coherence maintenance address queue assigning an available ID tag from a set of ID tags to an access committed to the shared memory for storage in said coherence maintenance address queue and retiring a coherence maintenance address queue entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding access, and
a comparator coupled to said input ports and said coherence maintenance address queue and receiving an address of a memory access request, said comparator comparing the address of the memory access request with all addresses stored in said coherence maintenance address queue and generating a hazard stall signal if the address of the memory access request matches any address stored in said coherence maintenance address queue.

### Claim 3 (depends on 2)

The data processing system of claim 2, wherein:
each of said plurality of coherence controllers further includes
a coherence transaction tracking queue having a plurality of entries, each entry storing dirty tags corresponding to coherence write data and an assigned ID tag,
a comparator connected to said coherence transaction tacking queue and receiving dirty tags corresponding to snoop response data, said comparator determining where snoop response dirty tags indicate dirty and said stored dirty tags indicate clean and inactive elsewhere, said comparator causing a write of received snoop response data that is dirty in the snoop response and clean in the coherence write data to the shared memory, and
wherein said ID allocation block is further coupled to said coherence transaction tracking queue and operable to assign an available ID tag from said set of ID tags upon creation of an entry within said coherence transaction tracking queue.

### Claim 4 (depends on 1)

The data processing system of claim 1, wherein:
each of said plurality of coherence controllers wherein
said ID allocation block assigns a lowest available ID tag upon allocating an ID tag.

### Claim 5 (depends on 1)

The data processing system of claim 1, wherein:
at least one of said plurality of endpoint memories includes a plurality of independently accessible memory banks.

### Claim 6 (depends on 5)

The data processing system of claim 5, wherein:
each of said plurality of independently accessible memory banks includes a plurality of virtual subbanks.