# US 2014/0156950 A1 · Emulated message signaled interrupts in multiprocessor systems

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0156950 A1
- Document ID: US20140156950A1
- Status: Published application
- Kind: A1
- Application number: 13/691,699
- Filed: 2012-11-30
- Published: 2014-06-05
- Earliest claimed: 2012-11-30
- Assignees: Intel Corporation
- Inventors: Yen Hsiang Chew
- Web page: https://patentgrep.com/patent/US20140156950A1

## CPC

- G06F 12/0831: using a bus scheme, e.g. with bus monitoring or watching means
- G06F 9/4812: {by interrupt, e.g. masked}
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 13/24: using interrupt (G06F13/32 takes precedence)
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A processor with coherency-leveraged support for low latency message signaled interrupt handling includes multiple execution cores and their associated cache memories. A first cache memory associated a first of the execution cores includes a plurality of cache lines. The first cache memory has a cache controller including hardware logic, microcode, or both to identify a first cache line as an interrupt reserved cache line and map the first cache line to a selected memory address associated with an I/O device. The selected system address may be a portion of configuration data in persistent storage accessible to the processor. The controller may set a coherency state of the first cache line to shared and, in response to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the selected memory address, emulate a first message signaled interrupt identifying the selected memory address.

## Claims

### Claim 1

A processor, comprising:
first storage to store configuration data indicating a memory address associated with an I/O device; and
a first processing core;
a first cache memory associated the first processing core, the first cache memory including:
a plurality of cache lines; and
a cache controller to:
identify a first cache line as an interrupt reserved cache line;
map the first cache line to the memory address;
set a coherency state of the first cache line to shared; and
emulate a first message signaled interrupt identifying the memory address responsive to detecting an I/O transaction includes I/O data from the I/O device and the I/O transaction includes a reference to the memory address.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the I/O transaction is a direct cache access transaction to the first cache memory and the reference to the memory address comprises an address, indicated in the I/O transaction, of the first cache line.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the I/O transaction is a direct cache access transaction to a second cache memory of a second core, detecting the I/O transaction comprises snooping the I/O transaction, and the reference to the memory address comprises an address of a second cache line, in the second cache memory, mapped to the memory address and shared with the first cache line.

### Claim 4 (depends on 3)

The processor of claim 3, wherein the cache controller generates a line fill request referencing the memory address responsive to snooping the I/O transaction and emulates the message signaled interrupt responsive to receiving the line fill.

### Claim 5 (depends on 4)

The processor of claim 4, wherein the second core initiates a flush of the second cache line responsive to snooping the line fill request and wherein the line fill request awaits completion of the flush.

### Claim 6 (depends on 1)

The processor of claim 1, wherein the I/O transaction comprises a direct memory access transaction to the memory address and wherein detecting the I/O transaction comprises snooping the I/O transaction.

### Claim 7 (depends on 6)

The processor of claim 6, wherein the cache controller generates a line fill request referencing the memory address responsive to snooping the I/O transaction and emulates the message signaled interrupt responsive to receiving the line fill.

### Claim 8 (depends on 1)

The processor of claim 1, wherein the cache controller emulates the first message signaled interrupt responsive the I/O data being written into the first cache line.

### Claim 9 (depends on 8)

The processor of claim 8, wherein the cache controller transitions the coherency state of the first cache line to an in-use coherency state, wherein the in-use coherency state indicates that an interrupt service routine corresponding to the emulated message signaled interrupt is executing.

### Claim 10 (depends on 9)

The processor of claim 9, wherein the I/O data includes an interrupt service routine vector and emulated interrupt data, wherein the interrupt service routine vector identifies an interrupt service routine and wherein the interrupt service routine, when executing, determines which of a plurality of processor is executing and accesses the emulated interrupt data.

### Claim 11 (depends on 10)

The processor of claim 10, wherein the emulated interrupt data includes a first portion and a second portion and wherein the interrupt service routine accesses the first portion when executed by first core executes and the interrupt service routine accesses the second portion when executed by a second core.

### Claim 12 (depends on 11)

The processor of claim 11, wherein the interrupt service routine performs a first function when executed by the first core and a second function, different than the first function, when executed by the second core.

### Claim 13 (depends on 11)

The processor of claim 11, wherein the interrupt service routine performs a function based on input data and wherein the first portion and the second portion indicate different input data.

### Claim 14

An interrupt handling method, comprising:
associating a memory address with an I/O device in a multiprocessor system;
reserving a first cache line of a first cache memory of a first processor for interrupt handling and mapping the first cache line to the memory address;
reserving a second cache line of a second cache memory of a second processor for interrupt handling and mapping the second cache line to the memory address;
initializing a coherency state of the first cache line and the second cache line to a shared coherency state;
responsive to detecting an I/O transaction containing I/O data from the I/O device and indicating a target address selected from: a direct address of the first cache line, a direct address of the second cache line, and the memory address:
storing I/O data in the memory address, the first cache line, and the second cache line;
emulating, by the first processor, a first emulated MSI referencing the selected system memory address responsive to storing the I/O data in the first cache line; and
emulating, by the second processor, a second emulated MSI referencing the selected system memory address responsive to storing the I/O data in the second cache line.

### Claim 15 (depends on 14)

The method of claim 14, wherein the I/O transaction comprises a direct memory address write transaction and the target address is the selected system memory address.

### Claim 16 (depends on 14)

The method of claim 14, wherein the I/O transaction comprises a direct cache address write transaction and the target address is the direct address of the first cache line.

### Claim 17 (depends on 14)

The method of claim 14, wherein the I/O data comprises posted write data, wherein the posted write data includes an interrupt service routine vector and emulated interrupt data, wherein the interrupt service routine vector indicates an interrupt service routine executed in response to an emulated MSI interrupt referencing the selected system memory address.

### Claim 18 (depends on 17)

The method of claim 17, wherein the emulated interrupt data includes a first portion and a second portion and wherein the interrupt service routine accesses the first portion when executed by the first processor and wherein the interrupt service routine accesses the second portion when executed by the second processor.

### Claim 19 (depends on 18)

The system of claim 18, wherein the interrupt service routine performs a first function when executed by the first processor and a second function, different than the first function, when executed by the second processor.

### Claim 20 (depends on 18)

The system of claim 18, wherein the interrupt service routine performs a function based on input data and wherein the first portion and the second portion indicate different input data.

### Claim 21

A computer system, comprising:
first storage including an operating system and I/O configuration data to indicate a memory address associated with an I/O device;
a processor;
an I/O hub to interface to the processor; and
an I/O device to interface to the I/O hub;
wherein the operating system includes:
processor-executable resume module instructions to reduce latency associated with transitioning from a power conservation state; and
processor executable connect module instructions to maintain a currency of a dynamic application during the power conservation state;
the processor includes a first core, comprising;
a first cache memory; and
a cache controller to:
reserve a first cache line of the first cache memory for message signaled interrupt processing;
map the first cache line to the memory address;
set a coherency state of the first cache line to shared; and
responsive to detecting an I/O transaction including I/O data from the I/O device and containing a reference to the memory address, emulate a first message signaled interrupt identifying the memory address.

### Claim 22 (depends on 21)

The system of claim 21, wherein the detecting of the I/O transaction comprises receiving a direct cache access from the I/O device and wherein the reference to the memory address comprises a direct address of the first cache line.

### Claim 23 (depends on 21)

The system of claim 21, wherein detecting the I/O transaction comprises snooping an I/O device direct cache access transaction to a second core of the processor and wherein the reference to the memory address comprises a direct address of a second cache line of a second cache memory, wherein the second cache line is reserved for interrupt handling and the processor maps to the memory address.

### Claim 24 (depends on 21)

The system of claim 21, wherein detecting the I/O transaction comprises snooping an I/O device direct memory access transaction addressing the memory address.

### Claim 25 (depends on 19)

The system of claim 19, wherein the I/O data includes an interrupt service routine vector identifying an interrupt service routine and emulated interrupt data accessed by the interrupt service routine to influence the execution of the interrupt service routine.

### Claim 26 (depends on 25)

The system of claim 25, wherein the emulated interrupt data includes a first portion accessed by the interrupt service routine during execution by the first core and a second portion accessed by the interrupt service routine during execution by the second core.