# US 2014/0156949 A1 · Fault handling in address translation transactions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156949 A1 - Document ID: US20140156949A1 - Status: Published application - Kind: A1 - Application number: 13/705,316 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Viswanath CHAKRALA; Timothy Nicholas Hay; Stuart David Biles - Web page: https://patentgrep.com/patent/US20140156949A1 ## CPC - G06F 12/0891: using clearing, invalidating or resetting means - G06F 11/073: {in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00)} - G06F 11/0793: {Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing apparatus having a memory configured to store tables having virtual to physical address translations, a cache configured to store a subset of the virtual to physical address translations and cache management circuitry configured to control transactions received from the processor requesting virtual address to physical address translations. The data processing apparatus identifies where a faulting transaction has occurred during execution of a context and whether the faulting transaction has a transaction stall or transaction terminate fault. The cache management circuitry is responsive to identification of the faulting transaction having a transaction terminate fault to invalidate all address translations in the cache that relate to the context of the faulting transaction such that a valid bit associated with each entry in the cache is set to invalid for the address translations. ## Claims ### Claim 1 A data processing apparatus comprising: a processor for processing a stream of instructions; a hierarchical memory system comprising a cache, a memory and cache management circuitry; said processor identifying storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said cache being to configured to store a subset of said virtual to physical address translations, said cache management circuitry being configured to control transactions received from said processor requesting virtual address to physical address translations; wherein said data processing apparatus is configured to identify where a faulting transaction has occurred during execution of a context and whether said faulting transaction has a transaction stall or transaction terminate fault; said cache management circuitry is configured: to respond to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault to invalidate all address translations in said cache that relate to said context of said faulting transaction such that a valid bit associated with each entry in said cache is set to invalid for said address translations, invalid entries being available for update and not forming part of any lookup in said cache; and to respond to identification of said faulting transaction and to said faulting transaction having a transaction stall fault to set a stall indicator associated with all address translations in said cache that relate to said context of said faulting transaction. ### Claim 2 (depends on 1) A data processing apparatus according to claim 1, wherein said cache comprises a table lookaside buffer and for each address translation comprises a virtual address, a corresponding physical address, a context identifier, a set of attributes, a valid bit and said stall indicator. ### Claim 3 (depends on 1) A data processing apparatus according to claim 1, wherein said data processing apparatus further comprises translation control circuitry comprising a control register configured to store previous context fault indicators for each context being processed, said previous context fault indicator bits indicating whether a next transaction in a context can proceed or cannot proceed. ### Claim 4 (depends on 3) A data processing apparatus according to claim 3, said cache management circuitry being configured to detect a faulting transaction for a context by detecting that said previous context fault indicator indicates that a next transaction in a context cannot proceed. ### Claim 5 (depends on 1) A data processing apparatus according to claim 1, wherein said data processing apparatus further comprises translation control circuitry comprising a control register configured to store context fault configuration indicators, said context fault configuration indicators indicating whether a fault is a stall fault. ### Claim 6 (depends on 5) A data processing apparatus according to claim 5, said cache management circuitry being configured to detect whether a faulting transaction has a terminate fault or a stall fault from said context fault configuration indicator. ### Claim 7 (depends on 1) A data processing apparatus according to claim 1, said cache management circuitry comprising a transaction queue for storing a plurality of pending transactions; said cache management circuitry being configured in response to receiving a transaction requesting a translation in said cache that has a stall indicator set, to stall said transaction by storing said transaction in said transaction queue and setting a stall indicator associated with said stored transaction, said cache management circuitry being configured to retain said transaction within said queue and not to allow said transaction to proceed further while said stall indicator is set. ### Claim 8 (depends on 7) A data processing apparatus according to claim 7, wherein said cache management circuitry is further configured in response to detecting said faulting transaction with said stall fault to store said faulting transaction with said stall fault in said transaction queue and to set said stall indicator associated with said stored transaction. ### Claim 9 (depends on 7) A data processing apparatus according to claim 7, said processor being configured to issue a resume instruction for a context that has been stalled when said context is to be resumed, said cache management circuitry being configured in response to said resume instruction to reset said stall indicator associated with said cache entries for said context and to reset said stall indicator associated with pending transactions of said context in said queue of transactions. ### Claim 10 (depends on 8) A data processing apparatus according to claim 8, said data processing apparatus further comprises translation control circuitry comprising a write only resume register configured to store a terminate or retry indicator, said resume register being configured to generate a control signal when written, said cache management circuitry being responsive to said control signal to either terminate said first stalled transaction in said transaction queue for said context or to reset said stall indicator associated with said transaction such that said transaction is retried in dependence upon said value written to said resume register and to reset said stall indicators associated with all other stalled transactions for said context. ### Claim 11 (depends on 3) A data processing apparatus according to claim 3, said processor being configured to issue a resume instruction for a context that has been stalled, said translation control circuitry being configured to update said previous context fault indicator for said context in response to said resume instruction. ### Claim 12 (depends on 1) A data processing apparatus according to claim 1, wherein said faulting transaction comprises one of an access flag fault, a permission fault, an external fault, a translation match conflict fault, a cache lock fault and an address size fault. ### Claim 13 (depends on 3) A data processing apparatus according to claim 3, further comprising page table walk control circuitry within said translation control circuitry, said memory management control circuitry being configured to transmit transactions requiring a page table walk from said transaction queue to said translation control circuitry and said translation control circuitry being configured to determine if a received transaction is for a context for which said previous context fault indicator is set and if it is said translation control circuitry is configured to terminate said transaction and if it is not said translation control circuitry is configured to forward said transaction to said page table walk table control circuitry. ### Claim 14 (depends on 7) A data processing apparatus according to claim 7, comprising a plurality of translation buffer units each comprising said cache, said cache management circuitry and said transaction queue, said data processing apparatus further comprising translation control circuitry comprising control registers and page table walk table control circuitry for controlling memory accesses to retrieve address translations from memory, each of said translation buffer units communicating with said translation control circuitry via a bus. ### Claim 15 A method of handling faults within address translation circuitry in a data processing apparatus, the data processing apparatus comprising: a processor for processing a stream of instructions; a hierarchical memory system comprising a cache a memory and cache management circuitry; said processor identifying storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said cache being configured to store a subset of said virtual to physical address translations, said cache management circuitry being configured to control transactions received from said processor requesting virtual address to physical address translations; said method comprising the steps of: identifying where a faulting transaction has occurred and whether said faulting transaction has a transaction stall or transaction terminate fault; responding to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault by invalidating all address translations in said cache that relate to said context of said faulting transaction; and responding to identification of said faulting transaction and to said faulting transaction having a transaction stall fault by setting a stall indicator associated with all address translations in said cache that relate to said context of said faulting transaction. ### Claim 16 (depends on 15) A method according to claim 15, comprising the further steps of: receiving a further transaction; looking for a translation for said transaction in said cache; in response to finding said translation in said cache with said stall indicator bit set forwarding said transaction to a transaction queue and setting a stall indicator associated with said transaction in said transaction queue; not issuing said transaction from said transaction queue until said stall bit is cleared. ### Claim 17 (depends on 15) A method according to claim 15, comprising the further steps of: receiving a further transaction; looking for a translation for said transaction in said cache; in response to not finding said translation in said cache forwarding said transaction to a transaction queue. ### Claim 18 (depends on 16) A method according to claim 16, comprising the further steps of: receiving a resume signal for a context; resetting said stall indicators associated with said entries in said cache for said context; and resetting said stall indicators associated with transactions in said queue for said context. ### Claim 19 (depends on 16) A method according to claim 16, comprising the further steps of: receiving a resume signal for a context, said resume signal including an indicator indicating whether said faulting stalled signal should be retried or terminated; resetting said stall indicators associated with said entries in said cache for said context; and determining said first stalled transaction for said context in said queue and either resetting said stall indicator associated with said transaction or terminating said transaction in dependence upon said indicator associated with said resume signal; and resetting said stall indicators associated with transactions in said queue for said context. ### Claim 20 A data processing apparatus comprising: processing means for processing a stream of instructions; a hierarchical memory system comprising a caching means, a memory and cache management means; said processor means identifying storage locations using virtual addresses and said memory system storing data using physical addresses, said memory being configured to store tables comprising virtual to physical address translations, said cache being for storing a subset of said virtual to physical address translations, said cache management means being for controlling transactions received from said processing means requesting virtual address to physical address translations; wherein said data processing apparatus is configured to identify where a faulting transaction has occurred during execution of a context and whether said faulting transaction has a transaction stall or transaction terminate fault; said cache management means is for: responding to identification of said faulting transaction and to said faulting transaction having a transaction terminate fault by invalidating all address translations in said cache that relate to said context of said faulting transaction such that a valid bit associated with each entry in said cache is set to invalid for said address translations, invalid entries being available for update and not forming part of any lookup in said cache; and for responding to identification of said faulting transaction and to said faulting transaction having a transaction stall fault by setting a stall indicator associated with all address translations in said cache that relate to said context of said faulting transaction.