# US 2014/0156948 A1 · Apparatuses and methods for pre-fetching and write-back for a segmented cache memory

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2014/0156948 A1
- Document ID: US20140156948A1
- Status: Published application
- Kind: A1
- Application number: 13/692,907
- Filed: 2012-12-03
- Published: 2014-06-05
- Earliest claimed: 2012-12-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: David Roberts; J. Thomas Pawlowski
- Web page: https://patentgrep.com/patent/US20140156948A1

## CPC

- G06F 12/0862: with prefetch
- G06F 12/0811: with multilevel cache hierarchies
- G06F 12/0895: of parts of caches, e.g. directory or tag array
- G06F 2212/283: Plural cache memories
- G06F 2212/602: Details relating to cache prefetching
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Apparatuses and methods for a cache memory are described. In an example method, a transaction history associated with a cache block is referenced, and requested information is read from memory. Additional information is read from memory based on the transaction history, wherein the requested information and the additional information are read together from memory. The requested information is cached in a segment of a cache line of the cache block and the additional information in cached another segment of the cache line. In another example, the transaction history is also updated to reflect the caching of the requested information and the additional information. In another example, read masks associated with the cache tag are referenced for the transaction history, the read masks identifying segments of a cache line previously accessed.

## Claims

### Claim 1

An apparatus, comprising:
a cache block configured to store information in a plurality of cache lines, each of the plurality of cache lines segmented into segments;
a memory configured to store a transaction history associated with the cache block;
a mask control coupled to the memory, the mask control configured to determine which segments of information for a cache line to read and/or write based at least in part on the transaction history; and
read and write-back logic coupled to the cache block and transaction history table, the read and write-back logic configured to execute transactions associated with the cache block.

### Claim 2 (depends on 1)

The apparatus of claim 1 wherein the transaction history comprises a plurality of read masks.

### Claim 3 (depends on 2)

The apparatus of claim 2 wherein the transaction history further comprises a plurality of write masks.

### Claim 4 (depends on 1)

The apparatus of claim 1 wherein the read and write-back logic is configured to execute a transaction for less than all of the segments of a cache line.

### Claim 5 (depends on 4)

The apparatus of claim 4 wherein the read and write-back logic is configured to execute a transaction for less than all of the segments of a cache line by using a memory mask.

### Claim 6 (depends on 1)

The apparatus of claim 1 wherein the cache block includes segment valid and dirty bits for each of the segments of a cache line.

### Claim 7 (depends on 1)

The apparatus of claim 1 wherein the cache block includes tag and valid/dirty bits for each one of the plurality of cache lines.

### Claim 8 (depends on 1)

The apparatus of claim 1 wherein the memory is included in a separate device from the mask control and read and write-back logic.

### Claim 9 (depends on 1)

The apparatus of claim 1, further comprising a timer configured to time a timeout period.

### Claim 10 (depends on 1)

The apparatus of claim 1 wherein the transaction history comprises a transaction history table stored by the memory.

### Claim 11 (depends on 10)

The apparatus of claim 10 wherein the transaction history table comprises a queue, table, cache, or combinations thereof.

### Claim 12 (depends on 10)

The apparatus of claim 10 wherein the transaction history table comprises a queue, the queue indexed according to memory addresses.

### Claim 13 (depends on 10)

The apparatus of claim 10 wherein the transaction history table comprises a table, the table indexed according to at least a portion of a memory address.

### Claim 14 (depends on 10)

The apparatus of claim 10 wherein the transaction history table comprises a cache, the cache indexed according to an index.

### Claim 15 (depends on 1)

The apparatus of claim 1, further comprising:
main memory coupled to the read and write-back logic and configured to store information.

### Claim 16 (depends on 15)

The apparatus of claim 15 wherein the memory configured to store the transaction history is part of the main memory.

### Claim 17 (depends on 15)

The apparatus of claim 15 wherein the memory configured to store the transaction history is separate from the main memory.

### Claim 18

An apparatus, comprising:
a cache block configured to store information in a plurality of cache lines, each of the plurality of cache lines segmented into segments; and
circuitry coupled to the cache block configured to allow for less than an entire cache line of information to be moved between a cache line of the plurality of cache lines and memory.

### Claim 19 (depends on 18)

The apparatus of claim 18, further comprising read and write-back logic coupled to the cache block and configured to execute transactions between the plurality of cache lines and memory.

### Claim 20 (depends on 19)

The apparatus of claim 19, further comprising main memory coupled to the read and write-back logic and configured to store information.

### Claim 21 (depends on 18)

The apparatus of claim 18, further comprising a mask control coupled to the cache block and configured to determine which segments of information for a cache line to read and/or write based at least in part on a transaction history for segments of the cache line.

### Claim 22 (depends on 18)

The apparatus of claim 18, further comprising a transaction history table configured to store transaction histories associated with segments of the cache block.

### Claim 23 (depends on 18)

The apparatus of claim 18, further comprising a transaction history table configured to store transaction histories associated with memory addresses.

### Claim 24 (depends on 18)

The apparatus of claim 18, further comprising a transaction history table configured to store transaction histories associated with cache lines.

### Claim 25 (depends on 18)

The apparatus of claim 18 wherein each of the segments for the plurality of cache lines is an N-byte segment, N being a multiple of 8.

### Claim 26

A method, comprising:
referencing transaction history associated with a cache block;
reading requested information from memory;
reading additional information from the memory based on the transaction history, wherein the requested information and the additional information are read together from the memory;
caching the requested information in a segment of a cache line of the cache block; and
caching the additional information in another segment of the cache line.

### Claim 27 (depends on 26)

The method of claim 26 wherein the requested information and the additional information read from memory is less than an entire cache line of information.

### Claim 28 (depends on 26)

The method of claim 26, further comprising updating the transaction history to reflect the caching of the requested information and the additional information.

### Claim 29 (depends on 26)

The method of claim 26 wherein referencing the transaction history comprises referencing a read mask.

### Claim 30 (depends on 26)

The method of claim 26, further comprising setting valid bits corresponding to the segments in which the requested information and the additional information are cached.

### Claim 31 (depends on 26)

The method of claim 26, further comprising clearing the transaction history responsive to a timeout period expiring.

### Claim 32 (depends on 31)

The method of claim 31, further comprising resetting the timeout period responsive to a segment hit for a read or write transaction.

### Claim 33

A method, comprising:
referencing transaction history associated with a cache block for information to be written to memory;
caching information from memory having the same cache tag as the information to be written in segments of a cache line, the selection of information from memory that is cached based at least in part on the transaction history;
writing the information to be written in a segment of the cache line; and
updating the transaction history to reflect the caching of the information to be written and the additional information.

### Claim 34 (depends on 33)

The method of claim 33, further comprising setting a dirty bit associated with the segment.

### Claim 35 (depends on 33)

The method of claim 33, further comprising:
writing the information to be written to memory responsive to evicting the cache line.

### Claim 36 (depends on 35)

The method of claim 35 wherein writing the information to be written to memory comprises writing less than a full cache line of information to memory.

### Claim 37 (depends on 33)

The method of claim 33 wherein referencing the transaction history comprises referencing write masks associated with the cache tag, the write masks identifying segments of a cache line previously written.

### Claim 38

A method, comprising:
referencing a transaction history associated with cache tag for information to be cached;
caching the information to be cached in a segment of a cache line;
determining additional information to cache in another segment of the cache line based on the transaction history;
caching the additional information in another segment of the cache line; and
updating the transaction history to reflect the caching of the information to be cached and the addition information.

### Claim 39 (depends on 38)

The method of claim 38 wherein referencing the transaction history comprises:
referencing read and write masks associated with the cache tag for the requested information.

### Claim 40 (depends on 39)

The method of claim 39, further comprising predicting information to be written to a main memory based at least in part on the write mask.

### Claim 41 (depends on 39)

The method of claim 39, further comprising preparing a non-volatile memory location for writing based at least in part on the write mask.

### Claim 42 (depends on 39)

The method of claim 39, further comprising precharging an open memory page in anticipation of a further write to a different page of memory based at least in part on the write mask.

### Claim 43 (depends on 38)

The method of claim 38, further comprising:
timing a timeout period or the cache line;
receiving a request for the information to be cached or the additional information;
determining a segment hit for the cache line; and
resetting the timeout period for the cache line responsive to the segment hit.

### Claim 44 (depends on 43)

The method of claim 43 wherein the request is a read request for the information to be cached or the additional information.

### Claim 45 (depends on 43)

The method of claim 43 wherein the request is a write request for the information to be cached or the additional information.

### Claim 46 (depends on 43)

The method of claim 43 wherein resetting the timeout period for the cache line responsive to the segment hit comprises resetting the timeout period for the cache line responsive to a segment write hit.

### Claim 47 (depends on 43)

The method of claim 43 wherein resetting the timeout period for the cache line responsive to the segment hit comprises resetting the timeout period for the cache line responsive to a segment read hit.