# US 2014/0156947 A1 · Method and apparatus for supporting a plurality of load accesses of a cache in a single cycle to maintain throughput > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156947 A1 - Document ID: US20140156947A1 - Status: Published application - Kind: A1 - Application number: 14/173,602 - Filed: 2014-02-05 - Published: 2014-06-05 - Earliest claimed: 2012-07-30 - Assignees: Soft Machines, Inc. - Applicants: Soft Machines, Inc. - Inventors: Karthikeyan AVUDAIYAPPAN; Sourabh ALURKAR - Web page: https://patentgrep.com/patent/US20140156947A1 ## CPC - G06F 12/0895: of parts of caches, e.g. directory or tag array - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for supporting a plurality of requests for access to a data cache memory (“cache”) is disclosed. The method comprises accessing a first set of requests to access the cache, wherein the cache comprises a plurality of blocks. Further, responsive to the first set of requests to access the cache, the method comprises accessing a tag memory that maintains a plurality of copies of tags for each entry in the cache and identifying tags that correspond to individual requests of the first set. The method also comprises performing arbitration in a same clock cycle as the accessing and identifying of tags, wherein the arbitration comprises: (a) identifying a second set of requests to access the cache from the first set, wherein the second set accesses a same block within the cache; and (b) selecting each request from the second set to receive data from the same block. ## Claims ### Claim 1 A method for supporting a plurality of requests for access to a data cache memory, said method comprising: accessing a first plurality of requests to access said data cache memory, wherein said data cache memory comprises a plurality of blocks; responsive to said first plurality of requests to access said data cache memory, accessing a tag memory that maintains a plurality of copies of tags for each entry in said data cache memory and identifying tags that correspond to individual requests of said first plurality of requests; and performing arbitration in a same clock cycle as said accessing said tag memory and said identifying tags, wherein said arbitration comprises: identifying a second plurality of requests to access said data cache memory from said first plurality of requests, wherein said second plurality of requests accesses a same block in a same cache-line within said data cache memory; and selecting each request from said second plurality of requests to receive data from said same block. ### Claim 2 (depends on 1) The method of claim 1, wherein said selecting further comprises: identifying a true winner and at least one bypass winner from said second plurality of requests, wherein said true winner accesses data from said same block directly and wherein said at least one bypass winner accesses data from said same block through a bypass path. ### Claim 3 (depends on 2) The method of claim 2, further comprising: accessing said data cache memory based on said tags that correspond to said individual requests, wherein both said true winner and said at least one bypass winner access data from said same block in a same cycle, and wherein both said true winner and said at least one bypass winner signal a Load Hit in said same cycle. ### Claim 4 The method of 2, wherein said bypass winner receives data via a bypass path from said true winner. ### Claim 5 (depends on 1) The method of claim 1, wherein said identifying a second plurality of requests comprises analyzing a set of lower address bits and a set of upper address bits of said first plurality of requests. ### Claim 6 (depends on 5) The method of claim 5, wherein said set of upper address bits are selected from a group consisting of: virtual tag bits and physical tag bits. ### Claim 7 (depends on 1) The method of claim 1, wherein at least one of said first plurality of requests is an unaligned load access request, and wherein said arbitration further comprises allowing said unaligned load access request to access multiple blocks within said data cache memory, wherein said multiple blocks comprise blocks straddled by an address of said unaligned load access request. ### Claim 8 A processor unit configured to perform a method for supporting a plurality of requests for access to a data cache memory, said method comprising: accessing a first plurality of requests to access said data cache memory, wherein said data cache memory comprises a plurality of blocks; responsive to said first plurality of requests to access said data cache memory, accessing a tag memory that maintains a plurality of copies of tags for each entry in said data cache memory and identifying tags that correspond to individual requests of said first plurality of requests; and performing arbitration in a same clock cycle as said accessing said tag memory and said identifying tags, wherein said arbitration comprises: identifying a second plurality of requests to access said data cache memory from said first plurality of requests, wherein said second plurality of requests accesses a same block in a same cache-line within said data cache memory; and selecting each request from said second plurality of requests to receive data from said same block. ### Claim 9 (depends on 8) The processor unit as described in claim 8, wherein said selecting further comprises: identifying a true winner and at least one bypass winner from said second plurality of requests, wherein said true winner accesses data from said same block directly and wherein said at least one bypass winner accesses data from said same block through a bypass path. ### Claim 10 (depends on 9) The processor unit as described in claim 9, wherein said method further comprises: accessing said data cache memory based on said tags that correspond to said individual requests, wherein both said true winner and said at least one bypass winner access data from said same block in a same cycle, and wherein both said true winner and said at least one bypass winner signal a Load Hit in said same cycle. ### Claim 11 (depends on 9) The processor unit as described in claim 9, wherein said bypass winner receives data via a bypass path from said true winner. ### Claim 12 (depends on 8) The processor unit as described in claim 8, wherein said identifying a second plurality of requests comprises analyzing a set of lower address bits and a set of upper address bits of said first plurality of requests. ### Claim 13 (depends on 8) The processor unit as described in claim 8, wherein said set of upper address bits are selected from a group consisting of: virtual tag bits and physical tag bits. ### Claim 14 (depends on 8) The processor unit as described in claim 8, wherein at least one of said first plurality of requests is an unaligned load access request, and wherein said arbitration further comprises allowing said unaligned load access request to access multiple blocks within said data cache memory, wherein said multiple blocks comprise blocks straddled by an address of said unaligned load access request. ### Claim 15 A computer system comprising: a memory; a processor communicatively coupled to said memory, wherein said processor is configured to process instructions out of order; and a cache system, comprising: a data cache memory configured to store blocks of data; a tag memory configured to stored tags that correspond to said blocks of data; and a cache controller operable to implement a method for supporting a plurality of requests for access to a data cache memory, said method comprising: accessing a first plurality of requests to access said data cache memory, wherein said data cache memory comprise a plurality of blocks; responsive to said first plurality of requests to access said data cache memory, accessing a tag memory that maintains a plurality of copies of tags for each entry in said data cache memory and identifying tags that correspond to individual requests of said first plurality of requests; and performing arbitration in a same clock cycle as said accessing said tag memory and said identifying tags, wherein said arbitration comprises: identifying a second plurality of requests to access said data cache memory from said first plurality of requests, wherein said second plurality of requests accesses a same block in a same cache-line within said data cache memory; and selecting each request from said second plurality of requests to receive data from said same block. ### Claim 16 (depends on 15) The system as described in claim 15, wherein said selecting further comprises: identifying a true winner and at least one bypass winner from said second plurality of requests, wherein said true winner accesses data from said same block directly and wherein said at least one bypass winner accesses data from said same block through a bypass path. ### Claim 17 (depends on 16) The system as described in claim 16, wherein said method further comprises: accessing said data cache memory based on said tags that correspond to said individual requests, wherein both said true winner and said at least one bypass winner access data from said same block in a same cycle, and wherein both said true winner and said at least one bypass winner signal a Load Hit in said same cycle. ### Claim 18 (depends on 16) The system as described in claim 16, wherein said bypass winner receives data via a bypass path from said true winner. ### Claim 19 (depends on 15) The system as described in claim 15, wherein said identifying a second plurality of requests comprises analyzing a set of lower address bits and a set of upper address bits of said first plurality of requests. ### Claim 20 (depends on 15) The system as described in claim 15, wherein at least one of said first plurality of requests is an unaligned load access request, and wherein said arbitration further comprises allowing said unaligned load access request to access multiple blocks within said data cache memory, wherein said multiple blocks comprise blocks straddled by an address of said unaligned load access request.