# US 2014/0156946 A1 · Memory prefetch systems and methods

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- Number: US 2014/0156946 A1
- Document ID: US20140156946A1
- Status: Published application
- Kind: A1
- Application number: 14/100,921
- Filed: 2013-12-09
- Published: 2014-06-05
- Earliest claimed: 2009-02-13
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Joe M. Jeddeloh
- Web page: https://patentgrep.com/patent/US20140156946A1

## CPC

- G06F 12/0875: with dedicated cache, e.g. instruction or stack
- G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode
- G06F 1/3275: {Power saving in memory, e.g. RAM, cache}
- G06F 12/0862: with prefetch
- G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Systems and methods are disclosed herein, including those that operate to prefetch a programmable number of data words from a selected memory vault in a stacked-die memory system when a pipeline associated with the selected memory vault is empty.

## Claims

### Claim 1

A memory system comprising:
a first memory vault comprising a first stacked plurality of memory arrays, each memory array in the first stacked plurality of memory arrays located on one of a plurality of stacked memory dies;
a second memory vault comprising a second stacked plurality of memory arrays, each memory array in the second stacked plurality of memory arrays located on one of the plurality of stacked memory dies; and
at least one controller communicatively coupled to at least one of the first and second memory vaults to provide at least one of control, switching, communication logic, or prefetch operations associated with at least one to the first and second memory vaults.

### Claim 2 (depends on 1)

The memory system of claim 1, further comprising:
a prefetch cache to store at least one cache line of read data.

### Claim 3 (depends on 2)

The memory system of claim 2, wherein the prefetch cache comprises a plurality of sets of prefetch buffers, each set of prefetch buffers comprising a cache line.

### Claim 4 (depends on 3)

The memory system of claim 3, wherein the least one controller is configured to selectively enable at least one cache line among the plurality of sets of prefetch buffers.

### Claim 5 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to issue a prefetch read request to the first memory vault when the first memory vault is idle.

### Claim 6 (depends on 5)

The memory system of claim 5, wherein the least one controller is configured to read at least one prefetch data word from a memory vault address corresponding to a data word read from the first memory vault in response to a previous read request.

### Claim 7 (depends on 5)

The memory system of claim 5, wherein the least one controller is configured to read at least one prefetch data word from a memory vault address selected from a range of addresses provided by a device issuing commands to the at least one controller.

### Claim 8 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to selectively enable prefetch operations.

### Claim 9 (depends on 1)

The memory system of claim 1, further comprising:
prefetch utilization logic communicatively coupled to the least one controller to track a number of cache line hits during a selected period of time.

### Claim 10 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to disable the prefetch operations if a hit rate associated with a prefetch cache is below a selected threshold for a first selected period of time.

### Claim 11 (depends on 10)

The memory system of claim 10, wherein the least one controller is configured to disable the prefetch operations for at least one of a second selected period of time or until a command to resume the prefetch operations is received from an originating device.

### Claim 12 (depends on 1)

The memory system of claim 1, further comprising:
prefetch write logic to update the first memory vault and a prefetch buffer with write data.

### Claim 13 (depends on 1)

The memory system of claim 1, further comprising:
prefetch read logic to read at least one prefetch word from at least one prefetch buffer if a read request received at the at least one controller references the at least one prefetch word.

### Claim 14 (depends on 1)

The memory system of claim 1, further comprising:
at least one of a voltage sensor or a temperature sensor at the first memory vault; and
a power monitor coupled to the voltage sensor or temperature sensor to provide an indication to the least one controller of a level of power consumption at the first memory vault.

### Claim 15 (depends on 14)

The memory system of claim 14, wherein the least one controller is configured to disable prefetch operations if the level of power consumption at the first memory vault is above a first selected threshold.

### Claim 16 (depends on 15)

The memory system of claim 15, wherein the least one controller is configured to re-enable the prefetch operations following at least one of a selected period of time, the level of power consumption dropping below a second selected threshold, or receipt of a command from an originating device to resume the prefetch operations.

### Claim 17 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to perform at least one of enabling and disabling the prefetch operations according to locality of data stream in the memory system.

### Claim 18 (depends on 1)

The memory system of claim 1, further comprising at least one prefetch buffer to store at least one prefetch data word associated with the prefetch read request.

### Claim 19 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to perform prefetch operations when a rate of cache line hits is greater than a selected rate.

### Claim 20 (depends on 1)

The memory system of claim 1, wherein the least one controller is configured to perform at least one of enabling and disabling prefetch operations associated with the first memory vault to target a selected power budget of the first memory vault.

### Claim 21 (depends on 1)

The memory system of claim 1, wherein at least one controller is located in a logic die.

### Claim 22 (depends on 21)

The memory system of claim 21, wherein the logic die is stacked with the plurality of stacked memory dies.