# US 2014/0156932 A1 · Eliminating fetch cancel for inclusive caches > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156932 A1 - Document ID: US20140156932A1 - Status: Published application - Kind: A1 - Application number: 13/706,321 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: James Dundas - Web page: https://patentgrep.com/patent/US20140156932A1 ## CPC - G06F 12/0862: with prefetch - G06F 12/0811: with multilevel cache hierarchies - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A method and apparatus for eliminating fetch cancels for inclusive caches are presented. Some embodiments of the apparatus include a first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache. The first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. Some embodiments of the method include preventing the first cache(s) from canceling issued fetch or prefetch requests to a second cache that is inclusive of the first cache(s). ## Claims ### Claim 1 An apparatus, comprising: at least one first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache, wherein said at least one first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. ### Claim 2 (depends on 1) The apparatus of claim 1, comprising a plurality of first caches configurable to issue fetch or prefetch requests to the second cache that is inclusive of the plurality of first caches, wherein the first caches are not permitted to cancel issued fetch or prefetch requests to the second cache. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the plurality of first caches comprises a plurality of data caches and a plurality of instruction caches, and wherein the plurality of first caches are associated with a corresponding plurality of processor cores. ### Claim 4 (depends on 3) The apparatus of claim 3, comprising the second cache, wherein the second cache is configurable to filter probes of the plurality of first caches. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the second cache comprises a plurality of inclusion bits, and wherein the second cache is configurable to set each inclusion bit to indicate that a corresponding line in the second cache is included in at least one of the plurality of first caches. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the second cache is configurable to filter probes of the plurality of first caches when an inclusion bit for a probed cache line is not set to indicate that the probed cache line is not included in at least one of the plurality of first caches. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein at least one first cache is configurable to issue speculative fetch or prefetch requests to the second cache, and wherein said at least one first cache is not permitted to cancel issued speculative fetch or prefetch requests to the second cache. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein said at least one first cache is not permitted to cancel issued fetch or prefetch requests in response to the issued fetch or prefetch being redirected due to a predicted-taken branch, a branch target address correction, or a redirect from the execution pipeline. ### Claim 9 A method, comprising: preventing at least one first cache from canceling issued fetch or prefetch requests to a second cache that is inclusive of said at least one first cache. ### Claim 10 (depends on 9) The method of claim 9, comprising preventing a plurality of first caches from canceling issued fetch or prefetch requests to the second cache. ### Claim 11 (depends on 10) The method of claim 10, wherein the plurality of first caches comprises a plurality of data caches and a plurality of instruction caches, and wherein the plurality of first caches are associated with a corresponding plurality of processor cores. ### Claim 12 (depends on 11) The method of claim 11, comprising filtering, at the second cache, probes of the plurality of first caches. ### Claim 13 (depends on 12) The method of claim 12, wherein the second cache comprises a plurality of inclusion bits, and wherein filtering the probes comprises setting at least one inclusion bit to indicate that at least one corresponding line in the second cache is included in at least one of the plurality of first caches. ### Claim 14 (depends on 13) The method of claim 13, wherein filtering the probes comprises filtering probes of the plurality of first caches when an inclusion bit for a probed cache line is not set to indicate that the probed cache line is not included in at least one of the plurality of first caches. ### Claim 15 (depends on 9) The method of claim 9, comprising issuing, from said at least one first cache, one or more speculative fetch or prefetch requests to the second cache, and preventing said at least one first cache from canceling issued speculative fetch or prefetch requests to the second cache. ### Claim 16 (depends on 15) The method of claim 15, comprising preventing said at least one first cache from canceling an issued fetch or prefetch request in response to the issued fetch or prefetch being redirected due to a predicted-taken branch, a branch target address correction, or a redirect from the execution pipeline. ### Claim 17 A computer readable media including instructions that when executed can configure a manufacturing process used to manufacture a semiconductor device comprising: at least one first cache configurable to issue fetch or prefetch requests to a second cache that is inclusive of said at least one first cache, wherein said at least one first cache is not permitted to cancel issued fetch or prefetch requests to the second cache. ### Claim 18 (depends on 17) The computer readable medium set forth in claim 17, wherein the instructions when executed can configure the manufacturing process used to manufacture the semiconductor device comprising the second cache, wherein the second cache is configurable to filter probes of the plurality of first caches.