# US 2014/0156931 A1 · State encoding for cache lines > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2014/0156931 A1 - Document ID: US20140156931A1 - Status: Published application - Kind: A1 - Application number: 13/706,159 - Filed: 2012-12-05 - Published: 2014-06-05 - Earliest claimed: 2012-12-05 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Robert Krick - Web page: https://patentgrep.com/patent/US20140156931A1 ## CPC - G06F 12/0811: with multilevel cache hierarchies - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and apparatus for state encoding of cache lines is described. Some embodiments of the method and apparatus support probing, in response to a first probe of a cache line in a first cache, a copy of the cache line in a second cache when the cache line is stale and the cache line is associated with a copy of the cache line stored in the second cache that can bypass notification of the first cache in response to modifying the copy of the cache line. ## Claims ### Claim 1 A method, comprising: in response to a first probe of a cache line in a first cache, probing a copy of the cache line in a second cache when the cache line is stale and the cache line is associated with a copy of the cache line stored in the second cache that can bypass notification of the first cache in response to modifying the copy of the cache line. ### Claim 2 (depends on 1) The method of claim 1, wherein the first cache is a higher level cache in a cache hierarchy that includes a plurality of lower level caches, and wherein the first cache is inclusive of the plurality of lower level caches, and wherein the plurality of lower level caches comprises the second cache. ### Claim 3 (depends on 1) The method of claim 1, comprising determining whether the cache line is stale based on a plurality of bits associated with the cache line. ### Claim 4 (depends on 3) The method of claim 3, comprising setting values of the plurality of bits to indicate that the cache line is in one of a plurality of states that indicate whether the cache line is stale. ### Claim 5 (depends on 4) The method of claim 4, wherein the plurality of states includes no more than eight states and the plurality of bits includes no more than three bits to represent the eight states. ### Claim 6 (depends on 1) The method of claim 1, comprising implementing a guard window that includes a time interval between receiving a downgrade probe and updating the value of the cache line in the first cache so that the cache line bypasses a stale state and transitions to a good state following the guard window. ### Claim 7 (depends on 1) The method of claim 1, comprising receiving the first probe, determining that the cache line is stale, probing the second cache, receiving information stored in the copy of the cache line in the second cache, and responding to the first probe based on the received information. ### Claim 8 (depends on 1) The method of claim 1, determining that the cache line is good because the cache line is not associated with a copy of the cache line in a second cache that can bypass notification of the first cache in response to modifying the copy of the first line. ### Claim 9 (depends on 8) The method of claim 8, comprising receiving the first probe, determining that the cache line is good, and responding to the first probe based on information stored in the cache line without probing the second cache in response to the first probe. ### Claim 10 An apparatus, comprising: a first cache configurable to probe, in response to a first probe of a cache line in a first cache, a copy of the cache line in a second cache when the cache line is stale and the cache line is associated with a copy of the cache line stored in the second cache that can bypass notification of the first cache in response to modifying the copy of the cache line. ### Claim 11 (depends on 10) The apparatus of claim 10, comprising a plurality of lower level caches in a cache hierarchy that comprises the first cache and the second cache, and wherein the first cache is a higher level cache that is inclusive of the plurality of lower level caches. ### Claim 12 (depends on 10) The apparatus of claim 10, comprising a plurality of state encoding bits associated with the cache line, and wherein the first cache is configurable to determine whether the cache line is stale based on the plurality of state encoding bits. ### Claim 13 (depends on 12) The apparatus of claim 12, wherein the first cache is configurable to set values of the plurality of state encoding bits to indicate that the cache line is in one of a plurality of states that indicate whether the cache line is stale. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the plurality of states includes no more than eight states and the plurality of state encoding bits includes no more than three bits to represent the eight states. ### Claim 15 (depends on 10) The apparatus of claim 10, comprising implementing a guard window that includes a time interval between receiving a downgrade probe and updating the value of the cache line in the first cache so that the cache line bypasses a stale state and transitions to a good state following the guard window. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein the first cache is configurable to receive the first probe, determine that the cache line is stale, probe the second cache, receive information stored in the copy of the cache line in the second cache, and respond to the first probe based on the received information. ### Claim 17 (depends on 10) The apparatus of claim 10, wherein the first cache is configurable to determine that the cache line is good because the cache line is not associated with a copy of the cache line in a second cache that can bypass notification of the first cache in response to modifying the copy of the first line. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the first cache is configurable to receive the first probe, determine that the cache line is good, and respond to the first probe based on information stored in the cache line without probing the second cache in response to the first probe. ### Claim 19 A computer readable media including instructions that when executed can configure a manufacturing process used to manufacture a semiconductor device comprising: a first cache configurable to probe, in response to a first probe of a cache line in a first cache, a copy of the cache line in a second cache when the cache line is stale and the cache line is associated with a copy of the cache line stored in the second cache that can bypass notification of the first cache in response to modifying the copy of the cache line. ### Claim 20 (depends on 19) The computer readable media set forth in claim 19, further comprising instructions that when executed can configure the manufacturing process used to manufacture the semiconductor device comprising a plurality of lower level caches in a cache hierarchy that comprises the first cache and the second cache, and wherein the first cache is a higher level cache that is inclusive of the plurality of lower level caches.